Fractional-N DLL for clock synchronization

Master'sMASTER OF ENGINEERIN

Programmable Active Mirror: A Scalable Decentralized Router

This work proposes and demonstrates the scalable router array that eliminates the internal centralization of conventional arrays, unlocking scalability, and the potential for a system composed of spatially separated elements that do not share a common timing reference. Architectural variations are presented, and their specific tradeoffs are discussed. The general operation, steering capabilities, signal and noise considerations, and timing control advantages are evaluated through analysis, simulation, and measurements. An element-level CMOS radio frequency integrated circuit (RFIC) is developed and used to demonstrate a four-element 25 GHz prototype router. The RFIC's programmable true time delay (TTD) control is used to correct path-length-difference-induced intersymbol interference (ISI) and improve a rerouted 270-Mb/s 64-QAM constellation from a completely scrambled state to an EVM of 4% rms (-28 dB). The prototype scalable router's concurrent dual-beam capabilities are demonstrated by simultaneously steering two full power beams at 24.9 and 25 GHz in two different directions in a free-space electromagnetic setup

A Bang-Bang All-Digital PLL for Frequency Synthesis

abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time.Dissertation/ThesisM.S. Electrical Engineering 201

Preliminary characterisation measurements of CERN picoTDC

In questa tesi sono presentate misure preliminari per valutare le prestazioni di un nuovo ASIC TDC sviluppato dal CERN (picoTDC) al fine di valutarne l'idoneità per l'implementazione all'interno del rilevatore TOF di ALICE. La parziale sostituzione dell'attuale HPTDC con il picoTDC comporterebbe, oltre al rinnovo dei componenti delle schede di lettura TDC sviluppate circa 20 anni fa, la semplificazione dell'architettura complessiva, consentendo l'integrazione di 64 canali per chip anziché gli 8 attuali dell'HPTDC. Per raggiungere questo obiettivo, sono stati eseguiti test mirati per valutare la risoluzione, la non linearità differenziale e la capacità di risposta ai segnali forniti dalla NINO FEA, la scheda di front-end del rivelatore TOF, del picoTDC. Dopo una breve introduzione alle varie tipologie di Analog to Digital Converter (ADC) e Time to Digital Converter (TDC), vengono presentate l'architettura del picoTDC e la configurazione sperimentale utilizzata, seguite dall'illustrazione dell'attività di ricerca condotta in laboratorio. I dati ottenuti hanno evidenziato una buona risoluzione del dispositivo (inferiore a 5 ps) e una notevole compatibilità con la scheda di front-end del rivelatore di ALICE. Tuttavia, i test sulla non linearità differenziale hanno mostrato risultati ancora insoddisfacenti. Pertanto, per il futuro, sarà necessario svolgere ulteriori approfondimenti al fine di migliorare la configurazione del chip

Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier

PhD ThesisAs further advances are made in semiconductor manufacturing technology the performance of circuits is continuously increasing. Unfortunately, as the technology node descends deeper into the nanometre region, achieving the potential performance gain is becoming more of a challenge; due not only to the effects of process variation but also to the reduced timing margins between signals within the circuit creating timing problems. Production Standard Automatic Test Equipment (ATE) is incapable of performing internal timing measurements due, first to the lack of accessibility and second to the overall timing accuracy of the tester which is grossly inadequate. To address these issue ‘on-chip’ time measurement circuits have been developed in a similar way that built in self-test (BIST) evolved for ‘on-chip’ logic testing. This thesis describes the design and analysis of three time amplifier circuits. The analysis undertaken considers the operational aspects related to gain and input dynamic range, together with the robustness of the circuits to the effects of process, voltage and temperature (PVT) variations. The design which had the best overall performance was subsequently compared to a benchmark design, which used the ‘buffer delay offset’ technique for time amplification, and showed a marked 6.5 times improvement on the dynamic range extending this from 40 ps to 300ps. The new design was also more robust to the effects of PVT variations. The new time amplifier design was further developed to include an adjustable gain capability which could be varied in steps of approximately 7.5 from 4 to 117. The time amplifier was then connected to a 32-stage tapped delay line to create a reconfigurable time measurement circuit with an adjustable resolution range from 15 down to 0.5 ps and a dynamic range from 480 down to 16 ps depending upon the gain setting. The overall footprint of the measurement circuit, together with its calibration module occupies an area of 0.026 mm2 The final circuit, overall, satisfied the main design criteria for ‘on-chip’ time measurement circuitry, namely, it has a wide dynamic range, high resolution, robust to the effects of PVT and has a small area overhead.Umm Al-Qura University

50-250MHZ ?S DLL for Clock Synchronization

Ph.DDOCTOR OF PHILOSOPH

Towards Very Large Scale Analog (VLSA): Synthesizable Frequency Generation Circuits.

Driven by advancement in integrated circuit design and fabrication technologies, electronic systems have become ubiquitous. This has been enabled powerful digital design tools that continue to shrink the design cost, time-to-market, and the size of digital circuits. Similarly, the manufacturing cost has been constantly declining for the last four decades due to CMOS scaling. However, analog systems have struggled to keep up with the unprecedented scaling of digital circuits. Even today, the majority of the analog circuit blocks are custom designed, do not scale well, and require long design cycles. This thesis analyzes the factors responsible for the slow scaling of analog blocks, and presents a new design methodology that bridges the gap between traditional custom analog design and the modern digital design. The proposed methodology is utilized in implementation of the frequency generation circuits – traditionally considered analog systems. Prototypes covering two different applications were implemented. The first synthesized all-digital phase-locked loop was designed for 400-460 MHz MedRadio applications and was fabricated in a 65 nm CMOS process. The second prototype is an ultra-low power, near-threshold 187-500 kHz clock generator for energy harvesting/autonomous applications. Finally, a digitally-controlled oscillator frequency resolution enhancement technique is presented which allows reduction of quantization noise in ADPLLs without introducing spurs.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/109027/1/mufaisal_1.pd

Radiation Hardened by Design Methodologies for Soft-Error Mitigated Digital Architectures

abstract: Digital architectures for data encryption, processing, clock synthesis, data transfer, etc. are susceptible to radiation induced soft errors due to charge collection in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Radiation hardening by design (RHBD) techniques such as double modular redundancy (DMR) and triple modular redundancy (TMR) are used for error detection and correction respectively in such architectures. Multiple node charge collection (MNCC) causes domain crossing errors (DCE) which can render the redundancy ineffectual. This dissertation describes techniques to ensure DCE mitigation with statistical confidence for various designs. Both sequential and combinatorial logic are separated using these custom and computer aided design (CAD) methodologies. Radiation vulnerability and design overhead are studied on VLSI sub-systems including an advanced encryption standard (AES) which is DCE mitigated using module level coarse separation on a 90-nm process with 99.999% DCE mitigation. A radiation hardened microprocessor (HERMES2) is implemented in both 90-nm and 55-nm technologies with an interleaved separation methodology with 99.99% DCE mitigation while achieving 4.9% increased cell density, 28.5 % reduced routing and 5.6% reduced power dissipation over the module fences implementation. A DMR register-file (RF) is implemented in 55 nm process and used in the HERMES2 microprocessor. The RF array custom design and the decoders APR designed are explored with a focus on design cycle time. Quality of results (QOR) is studied from power, performance, area and reliability (PPAR) perspective to ascertain the improvement over other design techniques. A radiation hardened all-digital multiplying pulsed digital delay line (DDL) is designed for double data rate (DDR2/3) applications for data eye centering during high speed off-chip data transfer. The effect of noise, radiation particle strikes and statistical variation on the designed DDL are studied in detail. The design achieves the best in class 22.4 ps peak-to-peak jitter, 100-850 MHz range at 14 pJ/cycle energy consumption. Vulnerability of the non-hardened design is characterized and portions of the redundant DDL are separated in custom and auto-place and route (APR). Thus, a range of designs for mission critical applications are implemented using methodologies proposed in this work and their potential PPAR benefits explored in detail.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201