A Bang-Bang All-Digital PLL for Frequency Synthesis

abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time.Dissertation/ThesisM.S. Electrical Engineering 201

Low jitter design techniques for monolithic CMOS phase-locked and delay-locked systems

Timing jitter is a major concern in almost every type of communication system. Yet the desire for high levels of integration works against minimization of this error, especially for systems employing a phase-locked loop (PLL) or delay-locked loop (DLL) for timing generation or timing recovery. There has been an increasing demand for fully-monolithic CMOS PLL and DLL designs with good jitter performance. In this thesis, the system level as well as the transistor level low jitter design techniques for integrated PLLs and DLLs have been explored.;On the system level, a rigorous jitter analysis method based on a z-domain model is developed, in which the jitter is treated as a random event. Combined with statistical methods, the rms value of the accumulated jitter can be expressed with a closed form solution that successfully ties the jitter performance with loop parameters. Based on this analysis, a cascaded PLL/DLL structure is proposed which combines the advantage of both loops. The resulting system is able to perform frequency synthesis with the jitter as low as that of a DLL.;As an efficient tool to predict the jitter performance of a PLL or DLL system, a new nonlinear behavioral simulator is developed based on a novel behavioral modeling of the VCO and delay-line. Compared with prior art, this simulator not only simplifies the computation but also enables the noise simulation. Both jitter performance during tracking and lock condition can be predicted. This is also the first reported top-level simulation tool for DLL noise simulation.;On the transistor level, three prototype chips for different applications were implemented and tested. The first two chips are the application of PLL in Gigabit fibre channel transceivers. High speed circuit blocks that have good noise immunity are the major design concern. Testing results show that both designs have met the specifications with low power dissipation. For the third chip, an adaptive on-chip dynamic skew calibration technique is proposed to realize a precise delay multi-phase clock generator, which is a topic that has not been addressed in previous work thus far. Experimental results strongly support the effectiveness of the calibration scheme. At the same time, this design achieves by far the best reported jitter performance

High performance CMOS amplifier and phase-locked loop design

Low voltage, high speed and high linearity are three different aspects of the analog circuit performance that designers are trying to achieve. In this dissertation, three design projects targeting these different performance optimizations are introduced.;The first work is a design of a low voltage operational amplifier. In this work, a threshold voltage tuning technique for low voltage CMOS analog circuit design is presented. A 750mV operational amplifier using this technique was designed in a 0.5mum 5V CMOS process with Vtp ≈ -0.9V and Vtn ≈ 0.8V. The active area is 560mum x 760mum. It exhibits a 62dB DC gain and consumes 38muW of power. It works with supply voltages from 0.75V to 1V. Compared to its 5V counterpart consuming the same amount of current, it maintains nearly the same gain bandwidth product of 3.7MHz. This op amp is the FIRST strong inversion op amp that works at a supply voltage below the threshold voltage.;The second is a design of a high speed phase-locked loop for data recovery. A new non-sequential linear phase detector is introduced in this work. Most of the existing phase detectors for data recovery are based on state-machines. The performance of these structures deteriorates rapidly at higher frequencies because of the inadequate settling performance of the flip-flop used to form the state machine. The new phase detector has a speed advantage over the state-machine based designs because it is simple and easy to implement in CMOS technology. Using this phase detector, a PLL was designed in a 0.25mum CMOS process with an active area of 400mum x 290mum. Experimental results show it successfully locks to a 2.1Gbit/s pseudo-random data sequence at 2.3V. It is believed that the architecture is the fastest that has been introduced for data recovery applications.;The third work introduces the design of a highly-linear variable gain amplifier. It achieves high linearity with third harmonic distortion better than -60dB Vopp = 1V at 160MHz in a 0.25mum CMOS process. It has a precise gain step of 6.02dB that is controlled digitally. The linearity performance is achieved with a linearized open loop amplifier configuration. Similar performance could only be achieved using feedback configuration before

데이터 전송로 확장성과 루프 선형성을 향상시킨 다중채널 수신기들에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 2. 정덕균.Two types of serial data communication receivers that adopt a multichannel architecture for a high aggregate I/O bandwidth are presented. Two techniques for collaboration and sharing among channels are proposed to enhance the loop-linearity and channel-expandability of multichannel receivers, respectively. The first proposed receiver employs a collaborative timing scheme recovery which relies on the sharing of all outputs of phase detectors (PDs) among channels to extract common information about the timing and multilevel signaling architecture of PAM-4. The shared timing information is processed by a common global loop filter and is used to update the phase of the voltage-controlled oscillator with better rejection of per-channel noise. In addition to collaborative timing recovery, a simple linearization technique for binary PDs is proposed. The technique realizes a high-rate oversampling PD while the hardware cost is equivalent to that of a conventional 2x-oversampling clock and data recovery. The first receiver exploiting the collaborative timing recovery architecture is designed using 45-nm CMOS technology. A single data lane occupies a 0.195-mm2 area and consumes a relatively low 17.9 mW at 6 Gb/s at 1.0V. Therefore, the power efficiency is 2.98 mW/Gb/s. The simulated jitter is about 0.034 UI RMS given an input jitter value of 0.03 UI RMS, while the relatively constant loop bandwidth with the PD linearization technique is about 7.3-MHz regardless of the data-stream noise. Unlike the first receiver, the second proposed multichannel receiver was designed to reduce the hardware complexity of each lane. The receiver employs shared calibration logic among channels and yet achieves superior channel expandability with slim data lanes. A shared global calibration control, which is used in a forwarded clock receiver based on a multiphase delay-locked loop, accomplishes skew calibration, equalizer adaptation, and the phase lock of all channels during a calibration period, resulting in reduced hardware overhead and less area required by each data lane. The second forwarded clock receiver is designed in 90-nm CMOS technology. It achieves error-free eye openings of more than 0.5 UI across 9− 28 inch Nelco 4000-6 microstrips at 4− 7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only 0.152 mm2 and consumes 69.8 mW, while the rest of the receiver occupies 0.297 mm2 and consumes 56 mW at a data rate of 7 Gb/s and a supply voltage of 1.35 V.1. Introduction 1 1.1 Motivations 1.2 Thesis Organization 2. Previous Receivers for Serial-Data Communications 2.1 Classification of the Links 2.2 Clocking architecture of transceivers 2.3 Components of receiver 2.3.1 Channel loss 2.3.2 Equalizer 2.3.3 Clock and data recovery circuit 2.3.3.1. Basic architecture 2.3.3.2. Phase detector 2.3.3.2.1. Linear phase detector 2.3.3.2.2. Binary phase detector 2.3.3.3. Frequency detector 2.3.3.4. Charge pump 2.3.3.5. Voltage controlled oscillator and delay-line 2.3.4 Loop dynamics of PLL 2.3.5 Loop dynamics of DLL 3. The Proposed PLL-Based Receiver with Loop Linearization Technique 3.1 Introduction 3.2 Motivation 3.3 Overview of binary phase detection 3.4 The proposed BBPD linearization technique 3.4.1 Architecture of the proposed PLL-based receiver 3.4.2 Linearization technique of binary phase detection 3.4.3 Rotational pattern of sampling phase offset 3.5 PD gain analysis and optimization 3.6 Loop Dynamics of the 2nd-order CDR 3.7 Verification with the time-accurate behavioral simulation 3.8 Summary 4. The Proposed DLL-Based Receiver with Forwarded-Clock 4.1 Introduction 4.2 Motivation 4.3 Design consideration 4.4 Architecture of the proposed forwarded-clock receiver 4.5 Circuit description 4.5.1 Analog multi-phase DLL 4.5.2 Dual-input interpolating deley cells 4.5.3 Dedicated half-rate data samplers 4.5.4 Cherry-Hooper continuous-time linear equalizer 4.5.5 Equalizer adaptation and phase-lock scheme 4.6 Measurement results 5. Conclusion 6. BibliographyDocto

최적 위상 검출 회로를 이용한 클럭 및 데이터 복원 회로에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 8. 김재하.Bang-bang phase detectors are widely used for today's high-speed communication circuits such as phase-locked loops (PLLs), delay-locked loops (DLLs) and clock-and-data recovery loops (CDRs) because it is simple, fast, accurate and amenable to digital implementations. However, its hard nonlinearity poses difficulties in design and analyses of the bang-bang controlled timing loops. Especially, dithering in bang-bang controlled CDRs sets conflicting requirements on the phase adjustment resolution as one tries to maximize the tracking bandwidth and minimize jitter. A fine phase step is helpful to minimize the dithering, but it requires circuits with finer resolution that consumes large power and area. In this background, this dissertation introduces an optimal phase detection technique that can minimize the effect of dithering without requiring fine phase resolution. A novel phase interval detector that looks for a phase interval enclosing the desired lock point is shown to find the optimal phase that minimizes the timing error without dithering. A digitally-controlled, phase-interpolating DLL-based CDR fabricated in 65nm CMOS demonstrates that it can achieve small area of 0.026mm^2 and low jitter of 41mUIp-p with a coarse phase adjustment step of 0.11UI, while dissipating only 8.4mW at 5Gbps. For the theoretic basis, various analysis techniques to understand bang-bang controlled timing loops are also presented. The proposed techniques are explained for both linearized loop and non-linear one, and applied to the evaluation of the proposed phase detection technique.1 Introduction 1 1.1 Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Contribution and Organization . . . . . . . . . . . . . . . . . 6 2 Pseudo-Linear Analysis of Bang-Bang Controlled Loops 9 2.1 Model of a Second-Order, Bang-Bang Controlled Timing Loop . . . 9 2.2 Necessary Condition for the Pseudo-Linear Analysis . . . . . . . . . 12 2.3 Derivation of Necessity Condition for the Pseudo-Linear Analysis . . 17 2.4 A Linearized Model of the Bang-Bang Phase Detector . . . . . . . . 18 2.5 Linearized Gain of a Bang-Bang Phase Detector for Jitter Transfer and Jitter Generation Analyses . . . . . . . . . . . . . . . . . . . . . 21 2.6 Jitter Transfer and Jitter Generation Analyses . . . . . . . . . . . . 29 2.7 Linearized Gains of a Bang-bang Phase Detector for Jitter Tolerance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8 Jitter Tolerance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 41 3 Nonlinear Analysis of Bang-Bang Controlled Loops 48 3.1 Transient Analysis of Bang-Bang Controlled Timing Loops . . . . . 48 3.2 Phase-portrait Analysis of Bang-Bang Controlled Timing Loops . . . 51 3.3 Markov-chain Analysis of Bang-Bang Controlled Timing Loops . . . 53 3.4 Analysis of Clock-and-Data Recovery Circuits . . . . . . . . . . . . . 57 3.4.1 Prediction of Bit-Error Rate . . . . . . . . . . . . . . . . . . 57 3.4.2 Eect of Transition Density . . . . . . . . . . . . . . . . . . . 58 3.4.3 Eect of Decimation . . . . . . . . . . . . . . . . . . . . . . . 61 3.4.4 Analysis of Oversampling Phase Detectors . . . . . . . . . . . 66 4 Design of Ditherless Clock and Data Recovery Circuit 75 4.1 Optimal Phase Detection . . . . . . . . . . . . . . . . . . . . . . . . 75 4.2 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.3 Analysis of the CDR with Phase Interval Detection . . . . . . . . . . 84 4.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.4.1 Sampling Receiver . . . . . . . . . . . . . . . . . . . . . . . . 89 4.4.2 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.4.3 Digital Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . 95 4.4.4 Phase Locked-Loop . . . . . . . . . . . . . . . . . . . . . . . . 98 4.4.5 Phase Interpolator . . . . . . . . . . . . . . . . . . . . . . . . 99 4.5 Built-In Self-Test Circuit for Jitter Tolerance Measurement . . . . . 102 4.6 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5 Conclusion 114 References 116Docto

Advanced techniques for fast offset cancellation limit amplifiers

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 87).As the need for higher data rates to end users increases, new technologies are required. Passive optical networks promise a vast improvement over previous methods, but they require amplifiers which can quickly adapt to changing input power levels. This thesis proposes two methods for addressing this problem, which are implementable in pure CMOS. Advanced modeling techniques allow for improvements on previous analog designs, resulting in a 50x improvement in signal acquisition time to 20ns. A novel digital design reduces this acquisition time even further. Results were verified using behavioral and component-level simulatorsby Carsten F. Jensen.M.Eng