From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Time-efficient fault detection and diagnosis system for analog circuits

Time-efficient fault analysis and diagnosis of analog circuits are the most important prerequisites to achieve online health monitoring of electronic equipments, which are involving continuing challenges of ultra-large-scale integration, component tolerance, limited test points but multiple faults. This work reports an FPGA (field programmable gate array)-based analog fault diagnostic system by applying two-dimensional information fusion, two-port network analysis and interval math theory. The proposed system has three advantages over traditional ones. First, it possesses high processing speed and smart circuit size as the embedded algorithms execute parallel on FPGA. Second, the hardware structure has a good compatibility with other diagnostic algorithms. Third, the equipped Ethernet interface enhances its flexibility for remote monitoring and controlling. The experimental results obtained from two realistic example circuits indicate that the proposed methodology had yielded competitive performance in both diagnosis accuracy and time-effectiveness, with about 96% accuracy while within 60 ms computational time.Peer reviewedFinal Published versio

Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks

While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements

NEXT-100 Technical Design Report (TDR). Executive Summary

In this Technical Design Report (TDR) we describe the NEXT-100 detector that will search for neutrinoless double beta decay (bbonu) in Xe-136 at the Laboratorio Subterraneo de Canfranc (LSC), in Spain. The document formalizes the design presented in our Conceptual Design Report (CDR): an electroluminescence time projection chamber, with separate readout planes for calorimetry and tracking, located, respectively, behind cathode and anode. The detector is designed to hold a maximum of about 150 kg of xenon at 15 bar, or 100 kg at 10 bar. This option builds in the capability to increase the total isotope mass by 50% while keeping the operating pressure at a manageable level. The readout plane performing the energy measurement is composed of Hamamatsu R11410-10 photomultipliers, specially designed for operation in low-background, xenon-based detectors. Each individual PMT will be isolated from the gas by an individual, pressure resistant enclosure and will be coupled to the sensitive volume through a sapphire window. The tracking plane consists in an array of Hamamatsu S10362-11-050P MPPCs used as tracking pixels. They will be arranged in square boards holding 64 sensors (8 times8) with a 1-cm pitch. The inner walls of the TPC, the sapphire windows and the boards holding the MPPCs will be coated with tetraphenyl butadiene (TPB), a wavelength shifter, to improve the light collection.Comment: 32 pages, 22 figures, 5 table