Computing the Largest Empty Rectangle

We consider the following problem: Given a rectangle containing N points, find the largest area subrectangle with sides parallel to those of the original rectangle which contains none of the given points. If the rectangle is a piece of fabric or sheet metal and the points are flaws, this problem is finding the largest-area rectangular piece which can be salvaged. A previously known result [13] takes $O(N^2 )$ worst-case and $O(N\log ^2 N)$ expected time. This paper presents an $O(N\log ^3 N)$ time, $O(N\log N)$ space algorithm to solve this problem. It uses a divide-and-conquer approach similar to the ones used by Bentley [1] and introduces a new notion of Voronoi diagram along with a method for efficient computation of certain functions over paths of a tree

Kinetic Voronoi Diagrams and Delaunay Triangulations under Polygonal Distance Functions

Let $P$ be a set of $n$ points and $Q$ a convex $k$-gon in ${\mathbb R}^2$. We analyze in detail the topological (or discrete) changes in the structure of the Voronoi diagram and the Delaunay triangulation of $P$, under the convex distance function defined by $Q$, as the points of $P$ move along prespecified continuous trajectories. Assuming that each point of $P$ moves along an algebraic trajectory of bounded degree, we establish an upper bound of $O(k^4n\lambda_r(n))$ on the number of topological changes experienced by the diagrams throughout the motion; here $\lambda_r(n)$ is the maximum length of an $(n,r)$-Davenport-Schinzel sequence, and $r$ is a constant depending on the algebraic degree of the motion of the points. Finally, we describe an algorithm for efficiently maintaining the above structures, using the kinetic data structure (KDS) framework

Rectilinear Steiner Tree Construction

The Minimum Rectilinear Steiner Tree (MRST) problem is to find the minimal spanning tree of a set of points (also called terminals) in the plane that interconnects all the terminals and some extra points (called Steiner points) introduced by intermediate junctions, and in which edge lengths are measured in the L1 (Manhattan) metric. This is one of the oldest optimization problems in mathematics that has been extensively studied and has been proven to be NP-complete, thus efficient approximation heuristics are more applicable than exact algorithms. In this thesis, we present a new heuristic to construct rectilinear Steiner trees (RSTs) with a close approximation of minimum length in Ο(n log n) time. To this end, we recursively divide a plane into a set of sub-planes of which optimal rectilinear Steiner trees (optRSTs) can be generated by a proposed exact algorithm called Const_optRST. By connecting all the optRSTs of the sub-planes, a sub-optimal MRST is eventually constructed. We show experimentally that for topologies with up to 100 terminals, the heuristic is 1.06 to 3.45 times faster than RMST, which is an efficient algorithm based on Prim’s method, with accuracy improvements varying from 1.31 % to 10.21 %

Automatische Platzierung von Beschriftung in Gebieten

Eine Beschriftung zu platzieren ist ein wesentlicher Teil, um Informationen graphisch darzustellen. Die Beschriftung von Karten ist aufwendige Arbeit, was dazu motiviert, diesen Prozess zu automatisieren. Hierfür werden einfache Gütekriterien angenommen: Die Beschriftung wird als Box repräsentiert. Es wird die größte Box innerhalb eines Polygons gesucht. In dieser Arbeit werden zwei entwickelte und implementierte Algorithmen beschrieben und untersucht, um Gebiete zu beschriften. In einem ersten Szenario wird eine Beschriftung in einem Gebiet gesucht, die parallel zu den Koordinatenachsen ist. Mit dem entwickelten Algorithmus lassen sich Beschriftungen effizient für beliebige Gebiete erzeugen. Im zweiten Szenario wird eine Beschriftung in einem Gebiet gesucht, die beliebig rotiert sein darf. Hierbei lassen sich Beschriftungen mit erheblichem Aufwand erzeugen. Praktisch können damit nur Beschriftungen für kleine Gebiete gefunden werden.Label placement is a significant part to represent information graphically. Labeling of maps is an expensive task which motivates to automate the process. For this purpose simple quality criteria are assumed: The label is represented as a box. Within a polygon, the largest box is searched. In this thesis two developed and implemented algorithms to label areas are described and tested. The first setting investigates the case of labels which are parallel to the coordinate axes. Using the algorithm labels can be generated efficiently for arbitrary areas. In the second setting an area label is searched which can be rotated arbitrarily. Here, labeling cost is considerable. In practice labels can be found only for small areas

Obstacle-avoiding rectilinear Steiner tree.

Li, Liang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.Includes bibliographical references (leaves 57-61).Abstract also in Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.1.1 --- Partitioning --- p.1Chapter 1.1.2 --- Floorplanning and Placement --- p.2Chapter 1.1.3 --- Routing --- p.2Chapter 1.1.4 --- Compaction --- p.3Chapter 1.2 --- Motivations --- p.3Chapter 1.3 --- Problem Formulation --- p.4Chapter 1.3.1 --- Properties of OARSMT --- p.4Chapter 1.4 --- Progress on the Problem --- p.4Chapter 1.5 --- Contributions --- p.5Chapter 1.6 --- Thesis Organization --- p.6Chapter 2 --- Literature Review on OARSMT --- p.8Chapter 2.1 --- Introduction --- p.8Chapter 2.2 --- Previous Methods --- p.9Chapter 2.2.1 --- OARSMT --- p.9Chapter 2.2.2 --- Shortest Path Problem with Blockages --- p.13Chapter 2.2.3 --- OARSMT with Delay Minimization --- p.14Chapter 2.2.4 --- OARSMT with Worst Negative Slack Maximization --- p.14Chapter 2.3 --- Comparison --- p.15Chapter 3 --- Heuristic Method --- p.17Chapter 3.1 --- Introduction --- p.17Chapter 3.2 --- Our Approach --- p.18Chapter 3.2.1 --- Handling of Multi-pin Nets --- p.18Chapter 3.2.2 --- Propagation --- p.20Chapter 3.2.3 --- Backtrack --- p.23Chapter 3.2.4 --- Finding MST --- p.26Chapter 3.2.5 --- Local Refinement Scheme --- p.26Chapter 3.3 --- Experimental Results --- p.28Chapter 3.4 --- Summary --- p.28Chapter 4 --- Exact Method --- p.32Chapter 4.1 --- Introduction --- p.32Chapter 4.2 --- Review on GeoSteiner --- p.33Chapter 4.3 --- Overview of our Approach --- p.33Chapter 4.4 --- FST with Virtual Pins --- p.34Chapter 4.4.1 --- Definition of FST --- p.34Chapter 4.4.2 --- Notations --- p.36Chapter 4.4.3 --- Properties of FST with Virtual Pins --- p.36Chapter 4.5 --- Generation of FST with Virtual Pins --- p.46Chapter 4.5.1 --- Generation of FST with Two Pins --- p.46Chapter 4.5.2 --- Generation of FST with 3 or More Pins --- p.48Chapter 4.6 --- Concatenation of FSTs with Virtual Pins --- p.50Chapter 4.7 --- Experimental Results --- p.52Chapter 4.8 --- Summary --- p.53Chapter 5 --- Conclusion --- p.55Bibliography --- p.6

VLSI Routing for Advanced Technology

Routing is a major step in VLSI design, the design process of complex integrated circuits (commonly known as chips). The basic task in routing is to connect predetermined locations on a chip (pins) with wires which serve as electrical connections. One main challenge in routing for advanced chip technology is the increasing complexity of design rules which reflect manufacturing requirements. In this thesis we investigate various aspects of this challenge. First, we consider polygon decomposition problems in the context of VLSI design rules. We introduce different width notions for polygons which are important for width-dependent design rules in VLSI routing, and we present efficient algorithms for computing width-preserving decompositions of rectilinear polygons into rectangles. Such decompositions are used in routing to allow for fast design rule checking. A main contribution of this thesis is an O(n) time algorithm for computing a decomposition of a simple rectilinear polygon with n vertices into O(n) rectangles, preseverving two-dimensional width. Here the two-dimensional width at a point of the polygon is defined as the edge length of a largest square that contains the point and is contained in the polygon. In order to obtain these results we establish a connection between such decompositions and Voronoi diagrams. Furthermore, we consider implications of multiple patterning and other advanced design rules for VLSI routing. The main contribution in this context is the detailed description of a routing approach which is able to manage such advanced design rules. As a main algorithmic concept we use multi-label shortest paths where certain path properties (which model design rules) can be enforced by defining labels assigned to path vertices and allowing only certain label transitions. The described approach has been implemented in BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics, University of Bonn, in cooperation with IBM. We present experimental results confirming that a flow combining BonnRoute and an external cleanup step produces far superior results compared to an industry standard router. In particular, our proposed flow runs more than twice as fast, reduces the via count by more than 20%, the wiring length by more than 10%, and the number of remaining design rule errors by more than 60%. These results obtained by applying our multiple patterning approach to real-world chip instances provided by IBM are another main contribution of this thesis. We note that IBM uses our proposed combined BonnRoute flow as the default tool for signal routing