Study of ionic contamination in electronic product assembly

Dissertação de mestrado em Chemical Analysis and Characterization TechniquesThe ever-growing demand for better PCB (printed circuit board) performance as well as component miniaturization and increasing density, are all challenges the automotive industry is facing nowadays. However, these alterations in the PCB layout alongside changes in production materials and techniques may jeopardize product reliability. One of the factors that has the ability to threaten PCB functioning is the introduction of ionic contaminants that increase the probability of electrochemical reactions and premature circuit failures. Methods have been created along the years in order to evaluate the presence of these contaminants on printed boards; one of them is the ROSE (Resistivity of Solvent Extract) test. This thesis aimed to study the ionic contamination in electronic product assembly using the CM22 contaminometer, a ROSE test machine. Essentially, this project was divided in two studies. The first one was the study of ROSE machine response and establishment of parameters to test its performance at Bosch Car Multimedia Portugal S.A. The results revealed that although the relation between the machine response and the dissolved contamination was linear, there was some disparity in values of PCBs from the same product family. The temperature and regeneration time of the extraction bath were identified as possible influencers of this discrepancy. Further tests showed temperature is not a significant factor for this behaviour and, at lower contamination levels, the regeneration time has little impact. The second study intended to evaluate the ionic contamination levels of printed circuit boards in 5 different stages of their production run. This research revealed that the ROSE levels of the PCBs obtained from the supplier decrease during the first steps of the process. Solder paste application, component insertion and reflow steps do not introduce much ionic residues on the board surface. Yet, the most important conclusion to this study is that the flux used for rework and selective soldering greatly increases surface contamination presence. In conclusion, the CM22 ROSE contaminometer is suitable to monitor processes in assembly plants. It can detect contamination trends at a process line and can be used as process control tool especially in a no-clean soldering process like the one used in Bosch. For this reason, the evaluation of ionic content should be carried out in different stages of PCBA production since it can be very deceptive to do them only after reflow process as it normally done.A crescente demanda por melhor desempenho de PCBs (placas de circuito impresso), bem como a miniaturização de componentes e o aumento da sua densidade, são desafios que a indústria automóvel enfrenta atualmente. No entanto, as alterações no seu design juntamente com as mudanças nos materiais e técnicas de produção podem comprometer a fiabilidade destas placas. Um dos fatores que tem a capacidade de ameaçar o funcionamento de um PCB é a introdução de contaminantes iónicos capazes de criar falhas elétricas no circuito. Vários métodos foram criados para avaliar a presença destes contaminantes em placas impressas; um deles é o teste ROSE (Resistividade do Extrato Solvente). Esta tese teve como objetivo o estudo da contaminação iónica na montagem de produtos eletrónicos utilizando o contaminometer CM22, um dispositivo de teste ROSE. Para isto, primeiro estudou-se a resposta da máquina ROSE e estabeleceu-se parâmetros para testar o seu desempenho na Bosch Car Multimedia Portugal S.A. Os resultados revelaram que embora a relação entre a resposta do aparelho e a contaminação dissolvida seja linear, existiu alguma disparidade nos valores de placas da mesma família. A temperatura e o tempo de regeneração do banho foram identificados como possíveis influenciadores desta discrepância. Testes adicionais mostraram que a temperatura não influencia este comportamento e, em níveis de contaminação mais baixos, o tempo de regeneração tem pouco impacto. O segundo estudo pretendia avaliar os níveis de contaminação iónica de placas de circuito impresso em 5 fases diferentes da sua montagem. Este estudo permitiu verificar que o PCB obtido do fornecedor possui um nível de ROSE que diminui ao longo dos primeiros passos do processo. As etapas de aplicação da pasta de solda, inserção dos componentes e refluxo não introduzem muitos resíduos à superfície da placa. No entanto, a conclusão mais importante deste estudo é que o fluxo usado para retrabalho e soldadura seletiva aumentam muito a contaminação na superfície das placas. Em conclusão, o contaminometer CM22 é adequado para monitorizar os processos de fabrico. Ele pode detetar tendências de contaminação na linha de produção e pode ser usado como ferramenta de controlo de processo, especialmente num processo sem limpeza como o da Bosch. Por esse motivo, a avaliação do conteúdo iónico deve ser realizada em diferentes etapas da produção de PCBAs, dado que pode ser enganoso fazê-lo somente após o refluxo, como normalmente é

On flexibly integrating machine vision inspection systems in PCB manufacture

The objective of this research is to advance computer vision techniques and their applications in the electronics manufacturing industry. The research has been carried out with specific reference to the design of automatic optical inspection (AOI) systems and their role in the manufacture of printed circuit boards (PCBs). To achieve this objective, application areas of AOI systems in PCB manufacture have been examined. As a result, a requirement for enhanced performance characteristics has been identified and novel approaches and image processing algorithms have been evolved which can be used within next generation of AOI systems. The approaches are based on gaining an understanding of ways in which manufacturing information can be used to support AOI operations. Through providing information support, an AOI system has access to product models and associated information which can be used to enhance the execution of visual inspection tasks. Manufacturing systems integration, or more accurately controlled access to electronic information, is the key to the approaches. Also in the thesis methods are proposed to achieve the flexible integration of AOI systems (and computer vision systems in general) within their host PCB manufacturing environment. Furthermore, potential applications of information supported AOI systems at various stages of PCB manufacturing have been studied. It is envisaged that more efficient and cost-effective applications of AOI can be attained through adopting the flexible integration methods proposed, since AOI-generated information can now be accessed and utilized by other processes

Modelling and simulation of paradigms for printed circuit board assembly to support the UK's competency in high reliability electronics

The fundamental requirement of the research reported within this thesis is the provision of physical models to enable model based simulation of mainstream printed circuit assembly (PCA) process discrete events for use within to-be-developed (or under development) software tools which codify cause & effects knowledge for use in product and process design optimisation. To support a national competitive advantage in high reliability electronics UK based producers of aircraft electronic subsystems require advanced simulation tools which offer model based guidance. In turn, maximization of manufacturability and minimization of uncontrolled rework must therefore enhance inservice sustainability for ‘power-by-the-hour’ commercial aircraft operation business models. [Continues.

A reference architecture for flexibly integrating machine vision within manufacturing

A reference architecture provides an overall framework that may embrace models, methodologies and mechanisms which can support the lifecycle of their target domain. The work described in this thesis makes a contribution to establishing such a generally applicable reference architecture for supporting the lifecycIe of a new generation of integrated machine vision systems. Contemporary machine vision systems consist of a complex combination of mechanical engineering, the hardware and software of an electronic processor, plus optical, sensory and lighting components. "This thesis is concerned with the structure of the software which characterises the system application. The machine vision systems which are currently used within manufacturing industry are difficult to integrate within the information systems required within modem manufacturing enterprises. They are inflexible in all but the execution of a range of similar operations, and their design and implementation is often such that they are difficult to update in the face of the required change inherent within modem manufacturing. The proposed reference architecture provides an overall framework within which a number of supporting models, design methodologies, and implementation mechanisms can combine to provide support for the rapid creation and maintenance of highly structured machine vision applications. These applications comprise modules which can be considered as building blocks of CIM systems. Their integrated interoperation can be enabled by the emerging infrastructural tools which will be required to underpin the next generation of flexibly integrated manufacturing systems. The work described in this thesis concludes that the issues of machine vision applications and the issues of integration of these applications within manufacturing systems are entirely separate. This separation is reflected in the structure of the thesis. PART B details vision application issues while PAIIT C deals with integration. The criteria for next generation integrated machine vision systems, derived in PART A of the thesis, are extensive. In order to address these criteria and propose a complete architecture, a "thin slice" is taken through the areas of vision application, and integration at the lifecycle stages of design, implementation, runtime and maintenance. The thesis describes the reference architecture, demonstrates its use though a proof of concept implementation and evaluates the support offered by the architecture for easing the problems of software change

A 64mW DNN-based Visual Navigation Engine for Autonomous Nano-Drones

Fully-autonomous miniaturized robots (e.g., drones), with artificial intelligence (AI) based visual navigation capabilities are extremely challenging drivers of Internet-of-Things edge intelligence capabilities. Visual navigation based on AI approaches, such as deep neural networks (DNNs) are becoming pervasive for standard-size drones, but are considered out of reach for nanodrones with size of a few cm${}^\mathrm{2}$. In this work, we present the first (to the best of our knowledge) demonstration of a navigation engine for autonomous nano-drones capable of closed-loop end-to-end DNN-based visual navigation. To achieve this goal we developed a complete methodology for parallel execution of complex DNNs directly on-bard of resource-constrained milliwatt-scale nodes. Our system is based on GAP8, a novel parallel ultra-low-power computing platform, and a 27 g commercial, open-source CrazyFlie 2.0 nano-quadrotor. As part of our general methodology we discuss the software mapping techniques that enable the state-of-the-art deep convolutional neural network presented in [1] to be fully executed on-board within a strict 6 fps real-time constraint with no compromise in terms of flight results, while all processing is done with only 64 mW on average. Our navigation engine is flexible and can be used to span a wide performance range: at its peak performance corner it achieves 18 fps while still consuming on average just 3.5% of the power envelope of the deployed nano-aircraft.Comment: 15 pages, 13 figures, 5 tables, 2 listings, accepted for publication in the IEEE Internet of Things Journal (IEEE IOTJ

An experimental assessment of computational fluid dynamics predictive accuracy for electronic component operational temperature

Ever-rising Integrated Circuit (IC) power dissipation, combined with reducing product development cycles times, have placed increasing reliance on the use of Computational Fluid Dynamics (CFD) software for the thermal analysis of electronic equipment. In this study, predictive accuracy is assessed for board-mounted electronic component heat transfer using both a CFD code dedicated to the thermal analysis of electronics, Flotherm, and a general-purpose CFD code, Fluent. Using Flotherm, turbulent flow modelling approaches typically employed for the analysis of electronics cooling, namely algebraic mixing length and two-equation high-Reynolds number k-e models, are assessed. As shown, such models are not specific for the analysis of forced airflows over populated electronic boards, which are typically classified as low-Reynolds number flows. The potential for improved predictive accuracy is evaluated using candidate turbulent flow models more suited to such flows, namely a one-equation SpalartAllmaras model, two-layer zonal model and two equation SST k-co model, all implemented in Fluent. Numerical predictions are compared with experimental benchmark data for a range of componentboard topologies generating different airflow phenomena and varying degrees of component thermal interaction. Test case complexity is incremented in controlled steps, from single board-mounted components in free convection, to forced air-cooled, multi-component board configurations. Apart from the prediction of component operational temperature, the application of CFD analysis to the design of electronic component reliability screens and convective solder reflow temperature profiles is also investigated. Benchmark criteria are based on component junction temperature and component-board surface temperature profiles, measured using thermal test chips and infrared thermography respectively. This data is supplemented by experimental visualisations of the forced airflows over the boards, which are used to help assess predictive accuracy. Component numerical modelling is based on nominal package dimensions and material thermal properties. To eliminate potential numerical modelling uncertainties, both the test component geometry and structural integrity are assessed using destructive and non-destructive testing. While detailed component modelling provides the à priori junction temperature predictions, the capability of compact thermal models to predict multi-mode component heat transfer is also assessed. In free convection, component junction temperature predictions for an in-line array of fifteen boardmounted components are within ±5°C or 7% of measurement. Predictive accuracy decays up to ±20°C or 35% in forced airflows using the k-e flow model. Furthermore, neither the laminar or k-e turbulent flow model accurately resolve the complete flow fields over the boards, suggesting the need for a turbulence model capable of modelling transition. Using a k-co model, significant improvements in junction temperature prediction accuracy are obtained, which are associated with improved prediction of both board leading edge heat transfer and component thermal interaction. Whereas with the k-e flow model, prediction accuracy would only be sufficient for the early to intermediate phase of a thermal design process, the use of the k-co model would enable parametric analysis of product thermal performance to be undertaken with greater confidence. Such models would also permit the generation of more accurate temperature boundary conditions for use in Physics-of-Failure (PoF) based component reliability prediction methods. The case is therefore made for vendors of CFD codes dedicated to the thermal analysis of electronics to consider the adoption of eddy viscosity turbulence models more suited to the analysis of component heat transfer. While this study ultimately highlights that electronic component operational temperature needs to be experimentally measured to quality product thermal performance and reliability, the use of such flow models would help reduce the current dependency on experimental prototyping. This would not only enhance the potential of CFD as a design tool, but also its capability to provide detailed insight into complex multi-mode heat transfer, that would otherwise be difficult to characterise experimentally

An Open Source and Open Hardware Deep Learning-Powered Visual Navigation Engine for Autonomous Nano-UAVs

Nano-size unmanned aerial vehicles (UAVs), with few centimeters of diameter and sub-10 Watts of total power budget, have so far been considered incapable of running sophisticated visual-based autonomous navigation software without external aid from base-stations, ad-hoc local positioning infrastructure, and powerful external computation servers. In this work, we present what is, to the best of our knowledge, the first 27g nano-UAV system able to run aboard an end-to-end, closed-loop visual pipeline for autonomous navigation based on a state-of-the-art deep-learning algorithm, built upon the open-source CrazyFlie 2.0 nano-quadrotor. Our visual navigation engine is enabled by the combination of an ultra-low power computing device (the GAP8 system-on-chip) with a novel methodology for the deployment of deep convolutional neural networks (CNNs). We enable onboard real-time execution of a state-of-the-art deep CNN at up to 18Hz. Field experiments demonstrate that the system's high responsiveness prevents collisions with unexpected dynamic obstacles up to a flight speed of 1.5m/s. In addition, we also demonstrate the capability of our visual navigation engine of fully autonomous indoor navigation on a 113m previously unseen path. To share our key findings with the embedded and robotics communities and foster further developments in autonomous nano-UAVs, we publicly release all our code, datasets, and trained networks

Investigation into Detection of Hardware Trojans on Printed Circuit Boards

The modern semiconductor device manufacturing flow is becoming increasingly vulnerable to malicious implants called Hardware Trojans (HT). With HTs becoming stealthier, a need for more accurate and efficient detection methods is becoming increasingly crucial at both Integrated Circuit (IC) and Printed Circuit Board (PCB) levels. While HT detection at an IC level has been widely studied, there is still very limited research on detecting and preventing HTs implanted on PCBs. In recent years the rise of outsourcing design and fabrication of electronics, including PCBs, to third parties has dramatically increased the possibility of malicious alteration and consequently the security risk for systems incorporating PCBs. Providing mechanical support for the electrical interconnections between different components, PCBs are an important part of electronic systems. Modern, complex and highly integrated designs may contain up to thirty layers, with concealed micro-vias and embedded passive components. An adversary can aim to modify the PCB design by tampering the copper interconnections or inserting extra components in an internal layer of a multi-layer board. Similar to its IC counterpart, a PCB HT can, among other things, cause system failure or leakage of private information. The disruptive actions of a carefully designed HT attack can have catastrophic implications and should therefore be taken seriously by industry, academia and the government. This thesis gives an account of work carried out in three projects concerned with HT detection on a PCB. In the first contribution a power analysis method is proposed for detecting HT components, implanted on the surface or otherwise, consuming power from the power distribution network. The assumption is that any HT device actively tampering or eavesdropping on the signals in the PCB circuit will consume electrical power. Harvesting this side-channel effect and observing the fluctuations of power consumption on the PCB power distribution network enables evincing the HT. Using a purpose-built PCB prototype, an experimental setup is developed for verification of the methodology. The results confirm the ability to detect alien components on a PCB without interference with its main functionality. In the second contribution the monitoring methodology is further developed by applying machine learning (ML) techniques to detect stealthier HTs, consuming power from I/O ports of legitimate ICs on the PCB. Two algorithms, One-Class Support Vector Machine (SVM) and Local Outlier Factor (LOF), are implemented on the legitimate power consumption data harvested experimentally from the PCB prototype. Simulation results are validated through real-life measurements and experiments are carried out on the prototype PCB. For validation of the ML classification models, one hundred categories of HTs are modelled and inserted into the datasets. Simulation results show that using the proposed methodology an HT can be detected with high prediction accuracy (F1-score at 99% for a 15 mW HT). Further, the developed ML model is uploaded to the prototype PCB for experimental validation. The results show consistency between simulations and experiments, with an average discrepancy of ±5.9% observed between One-Class SVM simulations and real-life experiments. The machine learning models developed for HT detection are low-cost in terms of memory (around 27 KB). In the third contribution an automated visual inspection methodology is proposed for detecting HTs on the surface of a PCB. It is based on a combination of conventional computer vision techniques and a dual tower Siamese Neural Network (SNN), modelled in a three stage pipeline. In the interest of making the proposed methodology broadly applicable a particular emphasis is made on the imaging modality of choice, whereby a regular digital optical camera is chosen. The dataset of PCB images is developed in a controlled environment of a photographic tent. The novelty in this work is that, instead of a generic production fault detection, the algorithm is optimised and trained specifically for implanted HT component detection on a PCB, be it active or passive. The proposed HT detection methodology is trained and tested with three groups of HTs, categorised based on their surface area, ranging from 4 mm² to 280 mm² and above. The results show that it is possible to reach effective detection accuracy of 95.1% for HTs as small as 4 mm². In case of HTs with surface area larger than 280 mm² the detection accuracy is around 96.1%, while the average performance across all HT groups is 95.6%

Development of an acoustic measurement system of the Modulus of Elasticity in trees, logs and boards

The objective of this Bachelor’s Thesis is to develop a portable electronic device capable of quantifying the stiffness of the wood of standing trees, logs and boards using non-destructive testing (NDT) by means of acoustic wave analysis. As an indicator of stiffness, the Modulus of Elasticity (MOE) is used, a standard figure in the industry. This way, wood from forestry can be characterized and classified for different purposes. This Thesis is part of LIFE Wood For Future, a project of the University of Granada (UGR) financed by the European Union’s LIFE programme. LIFE Wood For Future aims to recover the cultivation of poplar (populus sp.) in the Vega de Granada, by proving the quality of its wood through innovative structural bioproducts. Recovering the poplar groves of Granada would have great benefits for the Metropolitan Area: creation of local and sustainable jobs, improvement of biodiversity, and increase in the absorption of carbon dioxide in the long term, helping to reduce the endemic air pollution of Granada. This Final Degree Project has been developed in collaboration with the ADIME research group of the Higher Technical School of Building Engineering (ETSIE) and the aerospace electronics group GranaSat of the UGR. The goal of the developed device, named Tree Inspection Kit (or TIK), is to be an innovative, portable and easy-to-use tool for non-destructive diagnosis and classification of wood by measuring its MOE. TIK is equipped with the necessary electronics to quantify the Time of Flight (ToF) of an acoustic wave that propagates inside a piece of wood. In order to do this, two piezoelectric probes are used, nailed in the wood and separated a given distance longitudinally. The MOE can be derived from the propagation speed of the longitudinal acoustic wave if the density of the is known. For this reason, this device has the possibility of connecting a load cell for weighing logs or boards to estimate their density. It also has an expansion port reserved for future functionality. A methodology based on the Engineering Design Process (EDP) has been followed. The scope of this project embraces all aspects of the development of an electronic product from start to finish: conceptualization, specification of requirements, design, manufacture and verification. A project of this reach requires planning, advanced knowledge of signal analysis, electronics, design and manufacture of Printed Circuit Boards (PCB) and product design, as well as the development of a firmware for the embedded system, based on a RTOS. Prior to the design of the electronics, a Reverse Engineering process of some similar products of the competition is performed; as well as an exhaustive analysis of the signals coming from the piezoelectric sensors that are going to be used, and the frequency response characterization of the piezoelectric probes themselves. This project has as its ultimate goal the demonstration of the multidisciplinary knowledge of engineering, and the capacity of analysis, design and manufacturing by the author; his skill and professionalism in CAD and EDA software required for these tasks, as well as in the documentation of the entire process.El presente Trabajo de Fin de Grado tiene como objetivo el desarrollo de un dispositivo electrónico portátil capaz de cuantificar la rigidez de la madera de árboles en pie, trozas y tablas usando ensayos no destructivos (Non-Destructive Testing, NDT) por medio del análisis de ondas acústicas. Como indicador de la rigidez se usa el Módulo de Elasticidad (MOE), una figura estándar en la industria. Este TFG forma parte de LIFE Wood For Future, un proyecto de la Universidad de Granada (UGR) financiado por el programa LIFE de la Unión Europea. LIFEWood For Future tiene como objetivo recuperar el cultivo del chopo (populus sp.) en la Vega de Granada demostrando la viabilidad de su madera a través de bioproductos estructurales innovadores. Recuperar las choperas de Granada tendría grandes beneficios para la zona del Área Metropolitana: creación de puestos de trabajo locales y sostenibles, mejora de la biodiversidad, e incremento de la tasa de absorción de dióxido de carbono a largo plazo, contribuyendo a reducir la contaminación endémica del aire en Granada. Este Trabajo de Fin de Grado se ha desarrollado con la colaboración del grupo de investigación ADIME de la Escuela Técnica Superior de Ingeniería de Edificación (ETSIE) y el grupo de electrónica aeroespacial GranaSat de la UGR. El objetivo del dispositivo, denominado Tree Inspection Kit (TIK), es ser una herramienta innovadora, portátil y fácil de usar para el diagnóstico y clasificación no destructiva de la madera por medio de su MOE. TIK está dotado de la electrónica necesaria para medir el tiempo de tránsito (ToF) de una onda acústica que se propaga en el interior de una pieza de madera. Para ello, se utilizan dos sondas piezoeléctricas clavadas en la madera y separadas longitudinalmente una distancia conocida. De la velocidad de propagación de la onda longitudinal se puede derivar el MOE, previo conocimiento de la densidad del material. Por ello, este dispositivo cuenta con la posibilidad de conectarle una célula de carga y pesar trozas o tablas para estimar su densidad. También tiene un puerto de expansión reservado para funcionalidad futura. Se ha seguido una metodología basada en el Proceso de Diseño de Ingeniería (Engineering Design Process, EDP), abarcando todos los aspectos del desarrollo de un producto electrónico de principio a fin: conceptualización, especificación de requisitos, diseño, fabricación y verificación. Un proyecto de este alcance requiere de planificación, conocimientos avanzados de análisis de señales, de electrónica, de diseño y fabricación de Placas de Circuito Impreso (PCB) y de diseño de producto, así como el desarrollo de un firmware para el sistema empotrado, basado en un RTOS. Previo al diseño de la electrónica, se realiza un proceso de Ingeniería Inversa (Reverse Engineering) de algunos productos similares de la competencia; al igual que un exhaustivo análisis de las señales provenientes de los sensores piezoeléctricos que van a utilizarse y la caracterización en frecuencia de las propias sondas piezoeléctricas. Este proyecto tiene como fin último la demostración de los conocimientos multidisciplinares propios de la ingeniería y la capacidad de análisis, diseño y fabricación por parte del autor; su habilidad y profesionalidad en el software CAD y EDA requerido para estas tareas, así como en la documentación de todo el proceso.Unión Europe