Design of Novel Algorithm and Architecture for Gaussian Based Color Image Enhancement System for Real Time Applications

This paper presents the development of a new algorithm for Gaussian based color image enhancement system. The algorithm has been designed into architecture suitable for FPGA/ASIC implementation. The color image enhancement is achieved by first convolving an original image with a Gaussian kernel since Gaussian distribution is a point spread function which smoothen the image. Further, logarithm-domain processing and gain/offset corrections are employed in order to enhance and translate pixels into the display range of 0 to 255. The proposed algorithm not only provides better dynamic range compression and color rendition effect but also achieves color constancy in an image. The design exploits high degrees of pipelining and parallel processing to achieve real time performance. The design has been realized by RTL compliant Verilog coding and fits into a single FPGA with a gate count utilization of 321,804. The proposed method is implemented using Xilinx Virtex-II Pro XC2VP40-7FF1148 FPGA device and is capable of processing high resolution color motion pictures of sizes of up to 1600x1200 pixels at the real time video rate of 116 frames per second. This shows that the proposed design would work for not only still images but also for high resolution video sequences.Comment: 15 pages, 15 figure

Adaptive multichannel control of time-varying broadband noise and vibrations

This paper presents results obtained from a number of applications in which a recent adaptive algorithm for broadband multichannel active noise control is used. The core of the algorithm uses the inverse of the minimum-phase part of the secondary path for improvement of the speed of convergence. A further improvement of the speed of convergence is obtained by using double control filters for elimination of adaptation loop delay. Regularization was found to be necessary for robust operation. The regularization technique which is used preserves the structure to eliminate the adaptation loop delay. Depending on the application at hand, a number of extensions are used for this algorithm. For an application with rapidly changing disturbance spectra, the core algorithm was extended with an iterative affine projection scheme, leading to improved convergence rates as compared to the standard nomalized lms update rules. In another application, in which the influence of the parametric uncertainties was critical, the core algorithm was extended with low authority control loops operating at high sample rates. In addition, results of other applications are given, such as control of acoustic energy density and control of time-varying periodic and non-periodic vibrations

Rapidly converging multichannel controllers for broadband noise and vibrations

Applications are given of a preconditioned adaptive algorithm for broadband multichannel active noise control. Based on state-space descriptions of the relevant transfer functions, the algorithm uses the inverse of the minimum-phase part of the secondary path in order to improve the speed of convergence. A further improvement of the convergence rate is obtained by using double control filters for elimination of adaptation loop delay. Regularization was found to be essential for robust operation. The particular regularization technique preserves the structure to eliminate the adaptation loop delay. Depending on the application at hand, a number of extensions are used for this algorithm, such as for applications with rapidly changing disturbance spectra, applications with large parametric uncertainty, applications with control of time-varying acoustic energy density

An FPGA-based infant monitoring system

We have designed an automated visual surveillance system for monitoring sleeping infants. The low-level image processing is implemented on an embedded Xilinx’s Virtex II XC2v6000 FPGA and quantifies the level of scene activity using a specially designed background subtraction algorithm. We present our algorithm and show how we have optimised it for this platform

Hardware architecture implemented on FPGA for protecting cryptographic keys against side-channel attacks

This paper presents a new hardware architecture designed for protecting the key of cryptographic algorithms against attacks by side-channel analysis (SCA). Unlike previous approaches already published, the fortress of the proposed architecture is based on revealing a false key. Such a false key is obtained when the leakage information, related to either the power consumption or the electromagnetic radiation (EM) emitted by the hardware device, is analysed by means of a classical statistical method. In fact, the trace of power consumption (or the EM) does not reveal any significant sign of protection in its behaviour or shape. Experimental results were obtained by using a Virtex 5 FPGA, on which a 128-bit version of the standard AES encryption algorithm was implemented. The architecture could easily be extrapolated to an ASIC device based on standard cell libraries. The system is capable of concealing the real key when various attacks are performed on the AES algorithm, using two statistical methods which are based on correlation, the Welch’s t-test and the difference of means.Peer ReviewedPostprint (author's final draft

Chaotic image encryption using hopfield and hindmarsh–rose neurons implemented on FPGA

Chaotic systems implemented by artificial neural networks are good candidates for data encryption. In this manner, this paper introduces the cryptographic application of the Hopfield and the Hindmarsh–Rose neurons. The contribution is focused on finding suitable coefficient values of the neurons to generate robust random binary sequences that can be used in image encryption. This task is performed by evaluating the bifurcation diagrams from which one chooses appropriate coefficient values of the mathematical models that produce high positive Lyapunov exponent and Kaplan–Yorke dimension values, which are computed using TISEAN. The randomness of both the Hopfield and the Hindmarsh–Rose neurons is evaluated from chaotic time series data by performing National Institute of Standard and Technology (NIST) tests. The implementation of both neurons is done using field-programmable gate arrays whose architectures are used to develop an encryption system for RGB images. The success of the encryption system is confirmed by performing correlation, histogram, variance, entropy, and Number of Pixel Change Rate (NPCR) tests