Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of reconfigurable hardware such as FPGAs (Field Programmable Gate Array) embedded cryptographic hardware became cost-effective. Nevertheless, it is worthy to note that nowadays, even hardwired cryptographic algorithms are not so safe. From another side, the self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. Hardware acceleration significantly increases the performance of embedded systems built on programmable logic. Allowing a FPGA-based MicroBlaze processor to self-select the coprocessors uses can help reduce area requirements and increase a system's versatility. The architecture proposed in this paper is an optimal hardware implementation algorithm and takes dynamic partially reconfigurable of FPGA. This implementation is good solution to preserve confidentiality and accessibility to the information in the numeric communication

Physical 2D Morphware and Power Reduction Methods for Everyone

Dynamic and partial reconfiguration discovers more and more the focus in academic and industrial research. Modern systems in e.g. avionic and automotive applications exploit the parallelism of hardware in order to reduce power consumption and to increase performance. State of the art reconfigurable FPGA devices allows reconfiguring parts of their architecture while the other configured architecture stays undisturbed in operation. This dynamic and partial reconfiguration allows therefore adapting the architecture to the requirements of the application while run-time. The difference to the traditional term of software and its related sequential architecture is the possibility to change the paradigm of brining the data to the respective processing elements. Dynamic and partial reconfiguration enables to bring the processing elements to the data and is therefore a new paradigm. The shift from the traditional microprocessor approaches with sequential processing of data to parallel processing reconfigurable architectures forces to introduce new paradigms with the focus on computing in time and space

Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration

This paper presents an FPGA runtime framework that demonstrates the feasibility of using dynamic partial reconfiguration (DPR) for time-sharing an FPGA by multiple realtime computer vision pipelines. The presented time-sharing runtime framework manages an FPGA fabric that can be round-robin time-shared by different pipelines at the time scale of individual frames. In this new use-case, the challenge is to achieve useful performance despite high reconfiguration time. The paper describes the basic runtime support as well as four optimizations necessary to achieve realtime performance given the limitations of DPR on today's FPGAs. The paper provides a characterization of a working runtime framework prototype on a Xilinx ZC706 development board. The paper also reports the performance of realtime computer vision pipelines when time-shared

A remote demonstrator for dynamic FPGA reconfiguration

This paper presents a demonstrator for partial reconfiguration of FPGAs applied to image processing tasks. The main goal of the project is to develop an environment whichallows users to assess some of the advantages of using dynamic reconfiguration. The demonstration platform is built around a Xilinx Virtex-5 FPGA, which is used to implement a chain of four reconfigurable filters for processing images. Using a graphical interface, the user can choose which filter goes into which reconfigurable slot, submit images for processing and visualize the outcome of the whole process

Des terminaux green reconfigurables - vers une électronique durable

Vers une électronique durable ..

Real-time data coupling for hybrid testing in a geotechnical centrifuge

Geotechnical centrifuge models necessarily involve simplifications compared to the full-scale scenario under investigation. In particular, structural systems (e.g. buildings or foundations) generally can’t be replicated such that complex full-scale characteristics are obtained. Hybrid testing offers the ability to combine capabilities from physical and numerical modelling to overcome some of the experimental limitations. In this paper, the development of a coupled centrifuge-numerical model (CCNM) pseudo-dynamic hybrid test for the study of tunnel-building interaction is presented. The methodology takes advantage of the relative merits of centrifuge tests (modelling soil behaviour and soil-pile interactions) and numerical simulations (modelling building deformations and load redistribution), with pile load and displacement data being passed in real-time between the two model domains. To appropriately model the full-scale scenario, a challenging force-controlled system was developed (the first of its kind for hybrid testing in a geotechnical centrifuge). The CCNM application can accommodate simple structural frame analyses as well as more rigorous simulations conducted using the finite element analysis software ABAQUS, thereby extending the scope of application to non-linear structural behaviour. A novel data exchange method between ABAQUS and LabVIEW is presented which provides a significant enhancement compared to similar hybrid test developments. Data are provided from preliminary tests which highlight the capabilities of the system to accurately model the global tunnel-building interaction problem

Real-time data coupling for hybrid testing in a geotechnical centrifuge

Geotechnical centrifuge models necessarily involve simplifications compared to the full-scale scenario under investigation. In particular, structural systems (e.g. buildings or foundations) generally can’t be replicated such that complex full-scale characteristics are obtained. Hybrid testing offers the ability to combine capabilities from physical and numerical modelling to overcome some of the experimental limitations. In this paper, the development of a coupled centrifuge-numerical model (CCNM) pseudo-dynamic hybrid test for the study of tunnel-building interaction is presented. The methodology takes advantage of the relative merits of centrifuge tests (modelling soil behaviour and soil-pile interactions) and numerical simulations (modelling building deformations and load redistribution), with pile load and displacement data being passed in real-time between the two model domains. To appropriately model the full-scale scenario, a challenging force-controlled system was developed (the first of its kind for hybrid testing in a geotechnical centrifuge). The CCNM application can accommodate simple structural frame analyses as well as more rigorous simulations conducted using the finite element analysis software ABAQUS, thereby extending the scope of application to non-linear structural behaviour. A novel data exchange method between ABAQUS and LabVIEW is presented which provides a significant enhancement compared to similar hybrid test developments. Data are provided from preliminary tests which highlight the capabilities of the system to accurately model the global tunnel-building interaction problem

Suporte de sistema operacional para reconfiguração dinâmica de componentes de hardware para sistemas embarcados

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Ciência da Computação, Florianópolis, 2010As vantagens que podem ser obtidas com a utilização de computação reconfigurável são largamente conhecidas. No escopo de sistemas embarcados, a utilização dessa tecnologia pode trazer boas respostas para duas questões recorrentes na área: desempenho e consumo de energia. Contudo, sua utilização ainda está longe das prateleiras, limitando-se a incontáveis projetos de pesquisa. Isso se dá, em parte, pelo aumento da complexidade de desenvolvimento de tais sistemas. Uma maneira de diminuir a complexidade de desenvolvimento de sistemas embarcados é através de sistemas operacionais, que provêem abstrações, tanto de hardware quanto de software, para o desenvolvimento da aplicação e ainda permitem alcançar um nível maior de portabilidade da solução. Estendendo-se sistemas operacionais para dar suporte a hardware reconfigurável, provendo esses dispositivos como uma abstração de alto nível, pode-se diminuir a complexidade de desenvolvimento de sistemas embarcados reconfiguráveis. Com esse intuito, foi desenvolvido um suporte à reconfiguração de hardware no contexto do sistema operacional EPOS. Esse suporte estende o gerenciador de energia do EPOS, que permite a propagação de comandos para trocas de modo de operação pelos diversos componentes do sistema, para realizar as operações de hibernar e acordar o sistema como um todo. Essas operações são necessárias devido à utilização do método de diferenciação para gerar bitstreams parciais, o que produz resultados imprevisíveis que podem afetar o processador softcore sobre o qual o sistema operacional executa. Entretanto, tal abordagem possui vantagens que não podem ser ignoradas no contexto de sistemas embarcados, como simplificação significativa no projeto do hardware e melhor portabilidade da implementação do hardware entre diferentes modelos de FPGAs. A implementação presente neste trabalho mostra que pode-se chegar a uma plataforma arquiteturalmente independente, utilizando reconfiguração baseada em diferença, e sua viabilidade de utilização em sistemas embarcados reconfiguráveis.The advantages obtained by using reconfigurable computing are largely known. This technology can provide good answers for two recurring problems for embedded systems: performance and energy consumption. However, its utilization is happening almost exclusively in research projects, far away from the shelves. This is partially due to the increase of complexity for developing such systems. One way to diminish the development complexity of embedded systems is through operating systems, that provide software and hardware abstractions to the application development and improve the solution#s portability. By extending operating systems to support reconfigurable hardware, providing it as an high level system abstraction, the complexity of developing reconfigurable embedded systems can be reduced. With this intent, a reconfigurable hardware support was developed inside the EPOS operating system. This support extends EPOS# power manager, which propagates commands for operation mode changes through the system components, to allow the hibernation and wake up of the system. This operations are necessary due to the utilization of difference based partial reconfiguration, which produces unpredictable bitstream results that may affect the softcore processor that runs the operating system. Nevertheless, this approach presents some advantages that cannot be ignored when developing reconfigurable embedded systems, such as simplifying the hardware design and improving its portability between different FPGA models. The implementation in this work shows that we can reach an architecturally independent platform, using difference-based partial reconfiguration, and its feasibility in reconfigurable embedded systems