Development of a fully-depleted thin-body FinFET process

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT

Hot electron currents in MOSFETs.

Silicon has become the material of choice for fabrication of high circuit density, low defect density and high speed integration devices. CMOS technology has been favoured as an attractive candidate to take advantage of the performance enhancements available through miniturisation. However, hot carrier effects in general, and hot electron currents in particular, are posing as the main obstacle to a new era of sub-micron architecture in semiconductor device technology. Electron transport in modern sub-micron device is often governed by mechanisms that were not relevant to long-channel devices. Many of the classical device models are based upon such convenient assumptions as "thermal equilibrium" and "uniform local electric field". With the downscaling of devices, hot electron currents are becoming increasingly inherent. These currents arise from the fact that electrical fields in small geometry devices can reach very high values and can vary rapidly in space. The large electric field can Impart significant kinetic energies to the carriers. In thermal equilibrium, all elementary excitations in a semiconductor (eg. Electrons, holes, phonons) can be characterised by a temperature that is the same as the lattice temperature. Under the influence of large electric fields, however, the distribution function of these elementally excitations deviate from those in thermal equilibrium. The term "Hot Carriers" is often used to describe these non-equilibrium situations. In this thesis hot electron currents, in particular their physical origins and dependence upon various operational and geometrical parameters, have been discussed and then quantified in a number of models based on the "Lucky Drift" theory of transport. Temperature is then used as a tool to differentiate between the underlying physical processes, and to determine if reliability problems related to hot electron effects would improve under cryogenic operation. It has been the prime objective of this work from the outset to concentrate on the study of N-channel devices. This is primarily due to the fact that N-channel MOSFET's are more prone to hot electron effects, and therefore, studies in the nature of this enhanced susceptibility could prove to be more fruitful

Experimental study of electron velocity overshoot in silicon inversion layers

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Physics, 1994.Includes bibliographical references (leaves 127-133).by Hang Hu.Ph.D

Impact of intrinsic parameter fluctuations in ultra-thin body silicon-on-insulator MOSFET on 6-transistor SRAM cell

As CMOS device dimensions are being aggressively scaled, the device characteristic must be assessed against fundamental physical limits. Nanoscale device modelling and statistical circuit analysis is needed to provide designer with ability to explore innovative new MOSFET devices as well as understanding the limits of the scaling process. This work introduces a systematic simulation methodology to investigate the impact of intrinsic parameter fluctuation for a novel Ultra-Thin-Body (UTB) Silicon-on-Insulator (SOI) transistor on the corresponding device and circuits. It provides essential link between physical device-level numerical simulation and circuit-level simulation. A systematic analysis of the effects of random discrete dopants, body thickness variations and line edge roughness on a well scaled 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFET is performed. To fully realise the performance benefits of UTB-SOI based SRAM cells a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuations information into the compact model is developed. The impact of intrinsic parameter fluctuations on the stability and performance of 6T SRAM has been investigated. A comparison with the behaviour of a 6T SRAM based on a conventional 35 nm MOSFET is also presented

Quantum Mechanical Effects on MOSFET Scaling

This thesis describes advanced modeling of nanoscale bulk MOSFETs incorporating critical quantum mechanical effects such as gate direct tunneling and energy quantization of carriers. An explicit expression of gate direct tunneling for thin gate oxides has been developed by solving the Schroinger equation analytically. In addition, the impact of different gate electrode as well as gate insulation materials on the gate direct tunneling is explored. This results in an analytical estimation of the potential solutions to excessive gate leakage current. The energy quantization analysis involves the derivation of a quantum mechanical charge distribution model by solving the coupled Poisson and Schroinger equations. Based on the newly developed charge distribution model, threshold voltage and subthreshold swing models are obtained. A transregional drain current model which takes into account the quantum mechanical correction on device parameters is derived. Results from this model show good agreement with numeric simulation results of both long-channel and short-channel MOSFETs.The models derived here are used to project MOSFET scaling limits. Tunneling and quantization effects cause large power dissipation, low drive current, and strong sensitivities to process variation, which greatly limit CMOS scaling. Developing new materials and structures is imminent to extend the scaling process.Ph.D.Committee Chair: James D. Meindl; Committee Member: Ian F. Akyildiz; Committee Member: Philip First; Committee Member: Russell Dupuis; Committee Member: Willianm R. Calle

Probing the upper limits of current flow in one-dimensional carbon conductors

We use breakdown thermometry to study carbon nanotube (CNT) devices and graphene nanoribbons (GNRs) on SiO2 substrates. Experiments and modeling find the CNT-substrate thermal coupling scales proportionally to CNT diameter. Diffuse mismatch modeling (DMM) reveals the upper limit of thermal coupling ~0.7 WK 1m 1 for the largest diameter (3-4 nm) CNTs. Similarly, we extracted the GNR thermal conductivity (TC), ~80 (130) Wm 1K 1 at 20 (600) oC across our samples, dominated by phonons, with estimated <10% electronic contribution. The TC of GNRs is an order of magnitude lower than that of micron-sized graphene on SiO2, suggesting strong roles of edge and defect scattering, and the importance of thermal dissipation in small GNR devices. We also compare the peak current density of metallic single-walled CNTs with GNRs. We find that as the “footprint” (width) between such a device and the underlying substrate decreases, heat dissipation becomes more efficient (for a given width), allowing for higher current densities. Because of their smaller dimensions and lack of edges, CNTs can carry larger current densities than GNRs, up to ~16 mA/μm for an m-SWNT with a diameter of ~0.7 nm versus ~3 mA/μm for a GNR having a width of ~15 nm. Such cur-rent densities are the highest possible in any diffusive conductor, to our knowledge. We also study semiconducting and metallic single-walled CNTs under vacuum. Sem-iconducting single-wall CNTs under high electric field stress (~10 V/µm) display a re-markable current increase due to avalanche generation of free electrons and holes. Unlike in other materials, the avalanche process in such 1D quantum wires involves access to the third subband and is insensitive to temperature, but strongly dependent on diameter ~exp( 1/d 2). Comparison with a theoretical model yields a novel approach to obtain the inelastic optical phonon emission length, λOP,ems ≈ 15d nm. We find that current in metallic single-walled CNTs does not typically saturate, unlike previous observations which suggested a maximum current of ~25 μA. In fact, at very high fields (>10 V/μm) the current continues to increase with a slope ~0.5–1 μA/V, allowing m-CNTs to reach currents well in excess of 25 μA. Subsequent modeling sug-gests that carriers tunnel from the contacts into higher subbands. This allows currents to reach ~30–35 μA, which correspond to a current density of ~9 mA/μm for diameters of ~1.2 nm

Scaling and intrinsic parameter fluctuations in nanoCMOS devices

The core of this thesis is a thorough investigation of the scaling properties of conventional nano-CMOS MOSFETs, their physical and operational limitations and intrinsic parameter fluctuations. To support this investigation a well calibrated 35 nm physical gate length real MOSFET fabricated by Toshiba was used as a reference transistor. Prior to the start of scaling to shorter channel lengths, the simulators were calibrated against the experimentally measured characteristics of the reference device. Comprehensive numerical simulators were then used for designing the next five generations of transistors that correspond to the technology nodes of the latest International Technology Roadmap for Semiconductors (lTRS). The scaling of field effect transistors is one of the most widely studied concepts in semiconductor technology. The emphases of such studies have varied over the years, being dictated by the dominant issues faced by the microelectronics industry. The research presented in this thesis is focused on the present state of the scaling of conventional MOSFETs and its projections during the next 15 years. The electrical properties of conventional MOSFETs; threshold voltage (VT), subthreshold slope (S) and on-off currents (lon, Ioffi ), which are scaled to channel lengths of 35, 25, 18, 13, and 9 nm have been investigated. In addition, the channel doping profile and the corresponding carrier mobility in each generation of transistors have also been studied and compared. The concern of limited solid solubility of dopants in silicon is also addressed along with the problem of high channel doping concentrations in scaled devices. The other important issue associated with the scaling of conventional MOSFETs are the intrinsic parameter fluctuations (IPF) due to discrete random dopants in the inversion layer and the effects of gate Line Edge Roughness (LER). The variations of the three important MOSFET parameters (loff, VT and Ion), induced by random discrete dopants and LER have been comprehensively studied in the thesis. Finally, one of the promising emerging CMOS transistor architectures, the Ultra Thin Body (UTB) SOl MOSFET, which is expected to replace the conventional MOSFET, has been investigated from the scaling point of view

Simulation of hot carriers in semiconductor devices

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.Includes bibliographical references (p. 109-113).by Khalid Rahmat.Ph.D

Simulation of hot carriers in semiconductor devices

Includes bibliographical references (p. 109-113).Supported by the U.S. Navy. N00174-93-C-0035Khalid Rahmat