Transistor-Level Layout of Integrated Circuits

In this dissertation, we present the toolchain BonnCell and its underlying algorithms. It has been developed in close cooperation with the IBM Corporation and automatically generates the geometry for functional groups of 2 to approximately 50 transistors. Its input consists of a set of transistors, including properties like their sizes and their types, a specification of their connectivity, and parameters to flexibly control the technological framework as well as the algorithms' behavior. Using this data, the tool computes a detailed geometric realization of the circuit as polygonal shapes on 16 layers. To this end, a placement routine configures the transistors and arranges them in the plane, which is the main subject of this thesis. Subsequently, a routing engine determines wires connecting the transistors to ensure the circuit's desired functionality. We propose and analyze a family of algorithms that arranges sets of transistors in the plane such that a multi-criteria target function is optimized. The primary goal is to obtain solutions that are as compact as possible because chip area is a valuable resource in modern techologies. In addition to the core algorithms we formulate variants that handle particularly structured instances in a suitable way. We will show that for 90% of the instances in a representative test bed provided by IBM, BonnCell succeeds to generate fully functional layouts including the placement of the transistors and a routing of their interconnections. Moreover, BonnCell is in wide use within IBM's groups that are concerned with transistor-level layout - a task that has been performed manually before our automation was available. Beyond the processing of isolated test cases, two large-scale examples for applications of the tool in the industry will be presented: On the one hand the initial design phase of a large SRAM unit required only half of the expected 3 month period, on the other hand BonnCell could provide valuable input aiding central decisions in the early concept phase of the new 14 nm technology generation

Power Side Channels in Security ICs: Hardware Countermeasures

Power side-channel attacks are a very effective cryptanalysis technique that can infer secret keys of security ICs by monitoring the power consumption. Since the emergence of practical attacks in the late 90s, they have been a major threat to many cryptographic-equipped devices including smart cards, encrypted FPGA designs, and mobile phones. Designers and manufacturers of cryptographic devices have in response developed various countermeasures for protection. Attacking methods have also evolved to counteract resistant implementations. This paper reviews foundational power analysis attack techniques and examines a variety of hardware design mitigations. The aim is to highlight exposed vulnerabilities in hardware-based countermeasures for future more secure implementations

Sampled charge reuse for power reduction in switched capacitor data converters

Advances in semiconductor fabrication have enabled the shrinking of digital systems dramatically over the years. Although digital circuitry benefits tremendously from the constant shrinking of the device sizes, the benefits for analog circuits are not quite so dramatic. Low power is of critical importance in all mobile devices. Any reduction in power in the embedded analog-to-digital converters (ADCs) in such devices can help prolong the battery life. A technique is proposed that can be used to reduce power dissipation in ADCs that use switched-capacitor gain stages. It is shown for a pipeline ADC that the signal charge stored across the feedback capacitor from the first stage can be reused in the second stage at the end of the first stage\u27s amplify phase. The extra overhead of an extra capacitor is justified by the power savings of the proposed scheme;A well known approach for reducing the power dissipation in pipelined ADCs is the scaling down of capacitors progressively down the pipeline stream. The proposed technique combines the scaling of the capacitors with charge reuse. This combination inherits the power saving benefits of capacitor scaling and adds to the power saving by sharing the capacitor in two consecutive stages. Due to the highest power budget allocated to the first two stages, the sharing 2 is limited to the first two stages. Additionally, it is shown that the charge reuse results in reducing the total capacitive load driven by a stage\u27s opamp, potentially reducing the current requirements of the opamp;The proposed technique has been adapted for use in cyclic ADCs. The proposed technique reuses the charge from the first cycle in the next. This approach helps to reduce the die area of the capacitors in the switched capacitor network by up to 50%. Consequently, the power consumption requirement of the operational amplifier can be reduced. This is achieved while maintaining the thermal noise performance and conversion rate of the conventional structure. A 10-bit, 2.3MHz cyclic ADC using the new structure is implemented in 0.5mum CMOS. Spectre simulation results show a THD of -76dB and SFDR of -74.95dB

물리적 설계 자동화에서 표준셀 합성 및 최적화와 설계 품질 예측 방법론

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 2. 김태환.In the physical design of chip implementation, designing high-quality standard cell layout and accurately predicting post-route DRV (design rule violation) at an early stage is an important problem, especially in advanced technology nodes. This dissertation presents two methodologies that can contribute to improving the design quality and design turnaround time of physical design flow. Firstly, we propose an integrated approach to the two problems of transistor folding and placement in standard cell layout synthesis. Precisely, we propose a globally optimal algorithm of search tree based design space exploration, devising a set of effective speeding up techniques as well as dynamic programming based fast cost computation. In addition, our algorithm incorporates the minimum oxide diffusion jog constraint, which closely relies on both of transistor folding and placement. Through experiments with the transistor netlists and design rules in advanced node, our proposed method is able to synthesize fully routable cell layouts of minimal size within a very fast time for each netlist, outperforming the cell layout quality in the manual design. Secondly, we propose a novel ML based DRC hotspot prediction technique, which is able to accurately capture the combined impact of pin accessibility and routing congestion on DRC hotspots. Precisely, we devise a graph, called pin proximity graph, that effectively models the spatial information on cell I/O pins and the information on pin-to-pin disturbance relation. Then, we propose a new ML model, which tightly combines GNN (graph neural network) and U-net in a way that GNN is used to embed pin accessibility information abstracted from our pin proximity graph while U-net is used to extract routing congestion information from grid-based features. Through experiments with a set of benchmark designs using advanced node, our model outperforms the existing ML models on all benchmark designs within the fast inference time in comparison with that of the state-of-the-art techniques.칩 구현의 물리적 설계 단계에서, 높은 성능의 표준 셀 설계와 배선 연결 이후 조기에 설계 규칙 위반을 정확히 예측하는 것은 최신 공정에서 특히 중요한 문제이다. 본 논문에서는 물리적 설계에서의 설계 품질과 총 설계 시간 향상을 달성할 수 있는 두 가지 방법론을 제안한다. 먼저, 본 논문에서는 표준 셀 레이아웃 합성에서 트랜지스터 폴딩과 배치를 종합적으로 진행할 수 있는 방법론을 논한다. 구체적으로 탐색 트리 기반의 최적화 알고리즘과 동적 프로그래밍 기반 빠른 비용 계산 방법과 여러 속도 개선 기법을 제안한다. 여기에 더해, 최신 공정에서 트랜지스터 폴딩과 배치로 인해 발생할 수 있는 최소 산화물 확산 영역 설계 규칙을 고려하였다. 최신 공정에 대한 표준 셀 합성 실험 결과, 본 논문에서 제안한 방법이 설계 전문가가 수동으로 설계한 것 대비 높은 성능을 보이고, 설계 시간도 매우 짧음을 보인다. 두번째로, 본 논문에서는 셀 배치 단계에서 핀 접근성과 연결 혼잡으로 인한 영향을 종합적으로 고려할 수 있는 머신 러닝 기반 설계 규칙 위반 구역 예측 방법론을 제안한다. 먼저 표준 셀의 입/출력 핀의 물리적 정보와 핀과 핀 사이 방해 관계를 효과적으로 표현할 수 있는 핀 근접 그래프를 제안하고, 그래프 신경망과 유넷 신경망을 효과적으로 결합한 새로운 형태의 머신 러닝 모델을 제안한다. 이 모델에서 그래프 신경망은 핀 근접 그래프로부터 핀 접근성 정보를 추출하고, 유넷 신경망은 격자 기반 특징으로부터 연결 혼잡 정보를 추출한다. 실험 결과 본 논문에서 제안한 방법은 이전 연구들 대비 더 빠른 예측 시간에 더 높은 예측 성능을 달성함을 보인다.1 Introduction 1 1.1 Standard Cell Layout Synthesis 1 1.2 Machine Learning for Electronic Design Automation 6 1.3 Prediction of Design Rule Violation 8 1.4 Contributions of This Dissertation 11 2 Standard Cell Layout Synthesis of Advanced Nodes with Simultaneous Transistor Folding and Placement 14 2.1 Motivations 14 2.2 Algorithm for Standard Cell Layout Synthesis 16 2.2.1 Problem Definition 16 2.2.2 Overall Flow 18 2.2.3 Step 1: Generation of Folding Shapes 18 2.2.4 Step 2: Search-tree Based Design Space Exploration 20 2.2.5 Speeding up Techniques 23 2.2.6 In-cell Routability Estimation 28 2.2.7 Step 3: In-cell Routing 30 2.2.8 Step 4: Splitting Folding Shapes 35 2.2.9 Step 5: Relaxing Minimum-area Constraints 37 2.3 Experimental Results 38 2.3.1 Comparison with ASAP 7nm Cell Layouts 40 2.3.2 Effectiveness of Dynamic Folding 42 2.3.3 Effectiveness of Speeding Up Techniques 43 2.3.4 Impact of Splitting Folding Shape 48 2.3.5 Runtime Analysis According to Area Relaxation 51 2.3.6 Comparison with Previous Works 52 3 Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction using Graph Neural Network and U-Net 54 3.1 Preliminary 54 3.1.1 Graph Neural Network 54 3.1.2 Fully Convolutional Network 56 3.2 Proposed Prediction Methodology 57 3.2.1 Overall Flow 57 3.2.2 Pin Proximity Graph 58 3.2.3 Grid-based Features 61 3.2.4 Overall Architecture of PGNN 64 3.2.5 GNN Architecture in PGNN 64 3.2.6 U-net Architecture in PGNN 66 3.2.7 Final Prediction in PGNN 66 3.3 Experimental Results 68 3.3.1 Experimental Setup 68 3.3.2 Analysis on PGNN Performance 71 3.3.3 Comparison with Previous Works 72 3.3.4 Adaptation to Real-world Designs 81 3.3.5 Handling Data Imbalance Problem in Regression Model 86 4 Conclusions 92 4.1 Chapter 2 92 4.2 Chapter 3 93박

Standard Transistor Array (STAR). Volume 1: Placement technique

A large scale integration (LSI) technology, the standard transistor array uses a prefabricated understructure of transistors and a comprehensive library of digital logic cells to allow efficient fabrication of semicustom digital LSI circuits. The cell placement technique for this technology involves formation of a one dimensional cell layout and "folding" of the one dimensional placement onto the chip. It was found that, by use of various folding methods, high quality chip layouts can be achieved. Methods developed to measure of the "goodness" of the generated placements include efficient means for estimating channel usage requirements and for via counting. The placement and rating techniques were incorporated into a placement program (CAPSTAR). By means of repetitive use of the folding methods and simple placement improvement strategies, this program provides near optimum placements in a reasonable amount of time. The program was tested on several typical LSI circuits to provide performance comparisons both with respect to input parameters and with respect to the performance of other placement techniques. The results of this testing indicate that near optimum placements can be achieved by use of the procedures incurring severe time penalties

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers