An advanced Framework for efficient IC optimization based on analytical models engine

En base als reptes sorgits a conseqüència de l'escalat de la tecnologia, la present tesis desenvolupa i analitza un conjunt d'eines orientades a avaluar la sensibilitat a la propagació d'esdeveniments SET en circuits microelectrònics. S'han proposant varies mètriques de propagació de SETs considerant l'impacto dels emmascaraments lògic, elèctric i combinat lògic-elèctric. Aquestes mètriques proporcionen una via d'anàlisi per quantificar tant les regions més susceptibles a propagar SETs com les sortides més susceptibles de rebre'ls. S'ha desenvolupat un conjunt d'algorismes de cerca de camins sensibilitzables altament adaptables a múltiples aplicacions, un sistema lògic especific i diverses tècniques de simplificació de circuits. S'ha demostrat que el retard d'un camí donat depèn dels vectors de sensibilització aplicats a les portes que formen part del mateix, essent aquesta variació de retard comparable a la atribuïble a les variacions paramètriques del proces.En base a los desafíos surgidos a consecuencia del escalado de la tecnología, la presente tesis desarrolla y analiza un conjunto de herramientas orientadas a evaluar la sensibilidad a la propagación de eventos SET en circuitos microelectrónicos. Se han propuesto varias métricas de propagación de SETs considerando el impacto de los enmascaramientos lógico, eléctrico y combinado lógico-eléctrico. Estas métricas proporcionan una vía de análisis para cuantificar tanto las regiones más susceptibles a propagar eventos SET como las salidas más susceptibles a recibirlos. Ha sido desarrollado un conjunto de algoritmos de búsqueda de caminos sensibilizables altamente adaptables a múltiples aplicaciones, un sistema lógico especifico y diversas técnicas de simplificación de circuitos. Se ha demostrado que el retardo de un camino dado depende de los vectores de sensibilización aplicados a las puertas que forman parte del mismo, siendo esta variación de retardo comparable a la atribuible a las variaciones paramétricas del proceso.Based on the challenges arising as a result of technology scaling, this thesis develops and evaluates a complete framework for SET propagation sensitivity. The framework comprises a number of processing tools capable of handling circuits with high complexity in an efficient way. Various SET propagation metrics have been proposed considering the impact of logic, electric and combined logic-electric masking. Such metrics provide a valuable vehicle to grade either in-circuit regions being more susceptible of propagating SETs toward the circuit outputs or circuit outputs more susceptible to produce SET. A quite efficient and customizable true path finding algorithm with a specific logic system has been constructed and its efficacy demonstrated on large benchmark circuits. It has been shown that the delay of a path depends on the sensitization vectors applied to the gates within the path. In some cases, this variation is comparable to the one caused by process parameters variation

Transport and interaction effects in low-dimensional semiconductor heterostructures

The work in this thesis is related to the strongly correlated electron interaction effects taking place within 2D and 1D electron systems in IIIV semiconductor devices. Initially the work conducted on GaAs/AlGaAs was to investigate the effects of incompressible/compressible strips on the transverse and longitudinal resistance. Effects due to these strips lead to resistance anomalies in the transverse resistance, when the incompressible strips are in the evanescent regime, as described by the screening theory. In the study described in this thesis, such anomalies are observed not just for integer states, but for fractional states as well, i.e v = 4/3, 3/2, 5/3, 8/3, 3, 10/3, 7/2 and 5, which have been predicted theoretically but not studied experimentally. Additionally, longitudinal resistance hysteresis was noticed which increases in size with lower-valued v and by increasing the constriction of the quasi-1D channel within the system. The relaxation times of the longitudinal resistance within these hysteretic areas were found to be linked to two mechanisms with τ_1 and τ_2 being in the order of a 102 s and 106 s. These hysteretic loops were discussed in terms of dynamic nuclear polarisation and Ising ferromagnetism and the screening theory. It is discussed that the latter provides a better t in the explanation of the hysteresis. Further studies were conducted using the GaAs/AlGaAs device, but instead the transverse voltage was measured while setting up the system in measuring the quasi-1D conductance. By varying the Magnetic fi eld it was found that various oscillations were measured indicating unusual features. These oscillations seem to be linked to the 's in the 2DEG regions and the change in the peaks height and position are linked to the constriction size within the quasi-1D channel. These effects seem to be related to the crossings of Landau levels. In addition when spin-polarisation is enhanced a set of peaks increase in size compared to others, which is why it is thought that they are linked to enhanced spin polarisation within the constriction. By applying source-drain bias it was found that peaks that seem to be linked to even fi lling factors tend to disappear with positive voltage bias but for negative voltage bias, peaks related to both odd and even filling factors seem to persist. This is explained by scattering being induced due to quasi-elastic inter-Landau-level scattering as well as through the spin gap model. The data from these two chapters will provide a better understanding on the physical phenomena taking place and how the Landau levels and electron-electron interactions affect the behaviour of the systems. Furthermore the oscillations observed at 3.25 T are thought that they could be linked to the Aharonov-Bohm effect. Finally an InGaAs/InAlAs device was used to study the interaction effects due to perpendicular magnetic field and spin-orbit interactions within a quasi-1D channel. While applying lateral voltage bias within the quasi-1D channel, the asymmetric voltage on the split-gates acts as a type of electric Stern-Gerlach apparatus inducing spin-splitting as well as Rashba spin-orbit-coupling (RSOC). As a consequence exotic phases occur which lead to fractional conductance states appearing within the system, which are enhanced by increasing the magnetic fi eld. Such states are the 5/2 and 12/5 fractional states which if proven to be non-Abelian can help in the creation of topological fault tolerant quantum computers. These fractional conductance states are thought to be a consequence of backscattering and umklapp scattering. Also some of the fractional conductance states noticed have been observed experimentally in other 2D systems, and the fact that fractional states like 3/2, 5/2 and 7/2 weaken and strengthen with certain perpendicular magnetic fields and asymmetric voltages within the system are explained by the RSOC inducing in-plane magnetic fi eld components in the system leading to similar behaviour observed in 2D systems in tilted B-fi eld setups. In the InGaAs/InAlAs system though more fractional states appear in higher sub-band levels, compared to the measurements conducted in other two-dimensional systems, which is thought to be due to the intrinsically stronger spin-orbit coupling InGaAs/InAlAs systems have. These fractional states would be highly valuable for spintronic devices and the construction of quantum computers by utilising lower perpendicular magnetic fi elds than what is required in conventional 2D systems

Doctor of Philosophy

dissertationAdvancements in process technology and circuit techniques have enabled the creation of small chemical microsystems for use in a wide variety of biomedical and sensing applications. For applications requiring a small microsystem, many components can be integrated onto a single chip. This dissertation presents many low-power circuits, digital and analog, integrated onto a single chip called the Utah Microcontroller. To guide the design decisions for each of these components, two specific microsystems have been selected as target applications: a Smart Intravaginal Ring (S-IVR) and an NO releasing catheter. Both of these applications share the challenging requirements of integrating a large variety of low-power mixed-signal circuitry onto a single chip. These applications represent the requirements of a broad variety of small low-power sensing systems. In the course of the development of the Utah Microcontroller, several unique and significant contributions were made. A central component of the Utah Microcontroller is the WIMS Microprocessor, which incorporates a low-power feature called a scratchpad memory. For the first time, an analysis of scaling trends projected that scratchpad memories will continue to save power for the foreseeable future. This conclusion was bolstered by measured data from a fabricated microcontroller. In a 32 nm version of the WIMS Microprocessor, the scratchpad memory is projected to save ~10-30% of memory access energy depending upon the characteristics of the embedded program. Close examination of application requirements informed the design of an analog-to-digital converter, and a unique single-opamp buffered charge scaling DAC was developed to minimize power consumption. The opamp was designed to simultaneously meet the varied demands of many chip components to maximize circuit reuse. Each of these components are functional, have been integrated, fabricated, and tested. This dissertation successfully demonstrates that the needs of emerging small low-power microsystems can be met in advanced process nodes with the incorporation of low-power circuit techniques and design choices driven by application requirements

The Journal of Microelectronic Research

https://scholarworks.rit.edu/meec_archive/1015/thumbnail.jp

Design and test for timing uncertainty in VLSI circuits.

由於特徵尺寸不斷縮小，集成電路在生產過程中的工藝偏差在運行環境中溫度和電壓等參數的波動以及在使用過程中的老化等效應越來越嚴重，導致芯片的時序行為出現很大的不確定性。多數情況下，芯片的關鍵路徑會不時出現時序錯誤。加入更多的時序餘量不是一種很好的解決方案，因為這種保守的設計方法會抵消工藝進步帶來的性能上的好處。這就為設計一個時序可靠的系統提出了極大的挑戰，其中的一些關鍵問題包括：(一)如何有效地分配有限的功率預算去優化那些正爆炸式增加的關鍵路徑的時序性能；(二)如何產生能夠捕捉準確的最壞情況時延的高品質測試向量；(三)為了能夠取得更好的功耗和性能上的平衡，我們將不得不允許芯片在使用過程中出現一些頻率很低的時序錯誤。隨之而來的問題是如何做到在線的檢錯和糾錯。為了解決上述問題，我們首先發明了一種新的技術用於識別所謂的虛假路徑，該方法使我們能夠發現比傳統方法更多的虛假路徑。當將所提取的虛假路徑集成到靜態時序分析工具里以後，我們可以得到更為準確的時序分析結果，同時也能節省本來用於優化這些路徑的成本。接著，考慮到現有的延時自動向量生成(ATPG) 方法會產生功能模式下無法出現的測試向量，這種向量可能會造成測試過程中在被激活的路徑周圍出現過多(或過少)的電源噪聲(PSN) ，從而導致測試過度或者測試不足情況。為此，我們提出了一種新的偽功能ATPG工具。通過同時考慮功能約束以及電路的物理佈局信息，我們使用類似ATPG 的算法產生狀態跳變使其能最大化已激活的路徑周圍的PSN影響。最後，基於近似電路的原理，我們提出了一種新的在線原位校正技術，即InTimeFix，用於糾正時序錯誤。由於實現近似電路的綜合僅需要簡單的電路結構分析，因此該技術能夠很容易的擴展到大型電路設計上去。With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and aging effects. In most cases, these reliability threats manifest themselves as timing errors on speed-paths (i.e., critical or near-critical paths) of the circuit. Embedding a large design guard band to prevent timing errors to occur is not an attractive solution, since this conservative design methodology diminishes the benefit of technology scaling. This creates several challenges on build a reliable systems, and the key problems include (i) how to optimize circuit’s timing performance with limited power budget for explosively increased potential speed-paths; (ii) how to generate high quality delay test pattern to capture ICs’ accurate worst-case delay; (iii) to have better power and performance tradeoff, we have to accept some infrequent timing errors in circuit’s the usage phase. Therefore, the question is how to achieve online timing error resilience.To address the above issues, we first develop a novel technique to identify so-called false paths, which facilitate us to find much more false paths than conventional methods. By integrating our identified false paths into static timing analysis tool, we are able to achieve more accurate timing information and also save the cost used to optimize false paths. Then, due to the fact that existing delay automated test pattern generation (ATPG) methods may generate test patterns that are functionally-unreachable, and such patterns may incur excessive (or limited) power supply noise (PSN) on sensitized paths in test mode, thus leading to over-testing or under-testing of the circuits, we propose a novel pseudo-functional ATPG tool. By taking both circuit layout information and functional constrains into account, we use ATPG like algorithm to justify transitions that pose the maximized functional PSN effects on sensitized critical paths. Finally, we propose a novel in-situ correction technique to mask timing errors, namely InTimeFix, by introducing redundant approximation circuit with more timing slack for speed-paths into the design. The synthesis of the approximation circuit relies on simple structural analysis of the original circuit, which is easily scalable to large IC designs.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Yuan, Feng.Thesis (Ph.D.)--Chinese University of Hong Kong, 2012.Includes bibliographical references (leaves 88-100).Abstract also in Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Challenges to Solve Timing Uncertainty Problem --- p.2Chapter 1.2 --- Contributions and Thesis Outline --- p.5Chapter 2 --- Background --- p.7Chapter 2.1 --- Sources of Timing Uncertainty --- p.7Chapter 2.1.1 --- Process Variation --- p.7Chapter 2.1.2 --- Runtime Environment Fluctuation --- p.9Chapter 2.1.3 --- Aging Effect --- p.10Chapter 2.2 --- Technical Flow to Solve Timing Uncertainty Problem --- p.10Chapter 2.3 --- False Path --- p.12Chapter 2.3.1 --- Path Sensitization Criteria --- p.12Chapter 2.3.2 --- False Path Aware Timing Analysis --- p.13Chapter 2.4 --- Manufacturing Testing --- p.14Chapter 2.4.1 --- Functional Testing vs. Structural Testing --- p.14Chapter 2.4.2 --- Scan-Based DfT --- p.15Chapter 2.4.3 --- Pseudo-Functional Testing --- p.17Chapter 2.5 --- Timing Error Tolerance --- p.19Chapter 2.5.1 --- Timing Error Detection --- p.19Chapter 2.5.2 --- Timing Error Recover --- p.20Chapter 3 --- Timing-Independent False Path Identification --- p.23Chapter 3.1 --- Introduction --- p.23Chapter 3.2 --- Preliminaries and Motivation --- p.26Chapter 3.2.1 --- Motivation --- p.27Chapter 3.3 --- False Path Examination Considering Illegal States --- p.28Chapter 3.3.1 --- Path Sensitization Criterion --- p.28Chapter 3.3.2 --- Path-Aware Illegal State Identification --- p.30Chapter 3.3.3 --- Proposed Examination Procedure --- p.31Chapter 3.4 --- False Path Identification --- p.32Chapter 3.4.1 --- Overall Flow --- p.34Chapter 3.4.2 --- Static Implication Learning --- p.35Chapter 3.4.3 --- Suspicious Node Extraction --- p.36Chapter 3.4.4 --- S-Frontier Propagation --- p.37Chapter 3.5 --- Experimental Results --- p.38Chapter 3.6 --- Conclusion and Future Work --- p.42Chapter 4 --- PSN Aware Pseudo-Functional Delay Testing --- p.43Chapter 4.1 --- Introduction --- p.43Chapter 4.2 --- Preliminaries and Motivation --- p.45Chapter 4.2.1 --- Motivation --- p.46Chapter 4.3 --- Proposed Methodology --- p.48Chapter 4.4 --- Maximizing PSN Effects under Functional Constraints --- p.50Chapter 4.4.1 --- Pseudo-Functional Relevant Transitions Generation --- p.51Chapter 4.5 --- Experimental Results --- p.59Chapter 4.5.1 --- Experimental Setup --- p.59Chapter 4.5.2 --- Results and Discussion --- p.60Chapter 4.6 --- Conclusion --- p.64Chapter 5 --- In-Situ Timing Error Masking in Logic Circuits --- p.65Chapter 5.1 --- Introduction --- p.65Chapter 5.2 --- Prior Work and Motivation --- p.67Chapter 5.3 --- In-Situ Timing Error Masking with Approximate Logic --- p.69Chapter 5.3.1 --- Equivalent Circuit Construction with Approximate Logic --- p.70Chapter 5.3.2 --- Timing Error Masking with Approximate Logic --- p.72Chapter 5.4 --- Cost-Efficient Synthesis for InTimeFix --- p.75Chapter 5.4.1 --- Overall Flow --- p.76Chapter 5.4.2 --- Prime Critical Segment Extraction --- p.77Chapter 5.4.3 --- Prime Critical Segment Merging --- p.79Chapter 5.5 --- Experimental Results --- p.81Chapter 5.5.1 --- Experimental Setup --- p.81Chapter 5.5.2 --- Results and Discussion --- p.82Chapter 5.6 --- Conclusion --- p.85Chapter 6 --- Conclusion and Future Work --- p.86Bibliography --- p.10

Developing Organic Electrochemical Electronics from Fundamentals to Integrated Circuit Components

Heutzutage werden riesige Datenmengen zwischen Endgeräten und Cloud-Servern verschoben. Cloud-Computing war nach Bloomberg bereits für 1% des weltweiten Stromverbrauchs im Jahr 2021 verantwortlich. Darüber hinaus kann die monopolartige Speicherung personenbezogener Daten schwerwiegende Auswirkungen auf die Gesellschaften unserer Welt haben. Um persönlichen Datenschutz und einen nachhaltigen Energieverbrauch zu gewährleisten, bedarf es einer Datenverarbeitung direkt am Endgerät; bezeichnet als Edge Computing. In diesem Zuge wird die Nachfrage nach individuell gestalteten Edge-Geräten rapide ansteigen. Der neu entstehende Markt bietet der organischen elektrochemischen Elektronik eine große Chance, vor allem für bioelektronische Anwendungen; allerdings muss die Chipintegration verbessert werden. In dieser Arbeit habe ich elektrochemische organische Elektronik für die Integration in Computersysteme untersucht. Insbesondere habe ich einen festen, photostrukturierbaren Elektrolyten entwickelt, der die Integration von OECTs ohne Kreuzkommunikation zwischen Bauteilen ermöglicht. Die OECTs arbeiten bei Spannungen unter 1V und schalten mit einem großen An/Aus-Verhältnis von 5 Größenordnungen und einer Unterschwellenschwingung nahe des thermodynamischen Minimums von 60mV/Dekade. Darüber hinaus wurden bei der Untersuchung der Hysterese des Bauelements drei verschiedene Hystereseregime identifiziert. Anschließend untersuchte ich die Schaltdynamik des OECTs und demonstrierte ein Top-Gate-OECT mit einer maximalen Betriebsfrequenz von 1 kHz. Beim Versuch, die komplexe Wechselwirkung zwischen Ionen und Elektronen in integrierten OECTs zu verstehen, habe ich einen grundlegenden elektrochemischen Mechanismus identifiziert. Die Abhängigkeit dieses Mechanismus’ von der Gate-Größe und der Drain-Überlapplänge wurde aufgezeigt und dieses Wissen zur Optimierung elektrochemischer Inverter genutzt. Zur Darstellung von OECT-basierten Schaltungskomponenten habe ich verschiedene Halbleiter verwendet und entsprechende Inverter hergestellt. Schließlich wurde die Hysterese eines einzigen ambipolaren Inverters zur Demonstration eines dynamischen Klinkenschalters genutzt. Im Rahmen dieser Arbeit habe ich die OECT-Technologie von den Anfängen bis hin zu integrierten Schaltkreiskomponenten entwickelt. Ich glaube, dass diese Arbeit ein Startschuss für Wissenschaftler und Ingenieure sein wird, um die OECT-Technologie in der realen Welt des Edge Computing einzusetzen.Nowadays, vast amounts of data are shuttled between end-user devices and cloud servers. This cloud computing paradigm was, according to Bloomberg, already responsible for 1% of the world’s electricity usage in 2021. Moreover, the monopoly-like storage of personal data can have a severe impact on the world’s societies. To guarantee data privacy and sustainable energy consumption in future, data computation directly at the end-user site is mandatory. This computing paradigm is called edge computing. Owing to the vast amount of end-user-specific applications, the demand for individually designed edge devices will rapidly increase. In this newly approaching market, organic electrochemical electronics offer a great opportunity, especially for bioelectronic applications; however, the integration into low-power-consuming systems has to be improved. In this work, I investigated electrochemical organic electronics for their integration into computational systems. In particular, I developed a solid photopatternable electrolyte that allows integrating organic electrochemical transistors (OECTs) without cross-talk between adjacent devices. The OECTs operate at voltages below 1 V, and exhibit a large on/off ratio of 5 orders of magnitude and a subthreshold-swing close to the thermodynamic minimum of 60mV/dec. Moreover, investigating the device’s hysteresis, three distinct hysteresis regimes were identified; the RC-time-dominated regime I, the retention time governed regime II, and the time-independent stable regime III. I then examined the OECT’s switching dynamics and, subsequently, demonstrated a top-gate device with a maximum operating frequency of 1 kHz. Trying to understand the complex interaction between ions and electrons in integrated OECTs, I disclosed a fundamental electrochemical mechanism and named it the electrochemical electrode coupling (EEC). The EEC’s dependence on gate size and drain overlap length was rigorously shown, and this knowledge was used to optimize electrochemical inverters. Yet, to exemplify OECT-based circuit components, I employed various semiconductors and fabricated five inverters, each with its unique advantage. Finally, the ambipolar inverter’s hysteresis was used to demonstrate a single-device dynamic latch, a basic in-memory computational element. In this thesis, I developed the OECT technology from an infancy stage to integrated circuit components. I believe that this work will be a starting signal for scientists and engineers to bring the OECT technology into real-world edge computing

DEEP SUBMICRON CMOS VLSI CIRCUIT RELIABILITY MODELING, SIMULATION AND DESIGN

CMOS VLSI circuit reliability modeling and simulation have attracted intense research interest in the last two decades, and as a result almost all IC Design For Reliability (DFR) tools now try to incrementally simulate device wearout mechanisms in iterative ways. These DFR tools are capable of accurately characterizing the device wearout process and predicting its impact on circuit performance. Nevertheless, excessive simulation time and tedious parameter testing process often limit popularity of these tools in product design and fabrication. This work develops a new SPICE reliability simulation method that shifts the focus of reliability analysis from device wearout to circuit functionality. A set of accelerated lifetime models and failure equivalent circuit models are proposed for the most common MOSFET intrinsic wearout mechanisms, including Hot Carrier Injection (HCI), Time Dependent Dielectric Breakdown (TDDB), and Negative Bias Temperature Instability (NBTI). The accelerated lifetime models help to identify the most degraded transistors in a circuit in terms of the device's terminal voltage and current waveforms. Then corresponding failure equivalent circuit models are incorporated into the circuit to substitute these identified transistors. Finally, SPICE simulation is performed again to check circuit functionality and analyze the impact of device wearout on circuit operation. Device wearout effects are lumped into a very limited number of failure equivalent circuit model parameters, and circuit performance degradation and functionality are determined by the magnitude of these parameters. In this new method, it is unnecessary to perform a large number of small-step SPICE simulation iterations. Therefore, simulation time is obviously shortened in comparison to other tools. In addition, a reduced set of failure equivalent circuit model parameters, rather than a large number of device SPICE model parameters, need to be accurately characterized at each interim wearout process. Thus device testing and parameter extraction work are also significantly simplified. These advantages will allow circuit designers to perform quick and efficient circuit reliability analyses and to develop practical guidelines for reliable electronic designs

Structure and Electrical Characteristics of Graphene Field Effect Transistors

Työn tavoitteena oli tehdä kirjallisuuskatsaus grafeeni-transistoreista ja mallintaa Aalto Yliopiston Nanoteknologian tutkimusryhmän valmistamia grafeenikanavatransistoreja (engl. field-effect transistor). Työn alkuvaiheessa havaittiin, että kirjallisuudesta löytyy muutamia grafeenikanavatransistorimalleja, jotka pohjautuvat puolijohdekanavatransistoreihin. Työssä mitattiin grafeeni-kanavatransistorien DC-käyttäytymistä ja tarkoituksena oli tehdä radiotaajuusmittauksia SiC-grafeenitransistoreista sekä CVD grafeenitransistoreista. Radiotaajuusmittauksia ei kuitenkaan kyetty tekemään SiC-transistoreista, koska transistorien kontaktiresistanssi oli liian suuri ja näin ollen katkotaajuus liian alhainen. CVD-grafeenitransitoreille tehtiin S-parametrimittaukset ja laskettiin piensignaalimallin parametrit. CVD grafeenikanavatransistorien katkotaajuudeksi saatiin 80 MHz, joka on samaa suuruusluokkaa laskennallisen katkotaajuuden kanssa. Työssä käytettiin jo olemassaolevaamallia transistorin DC-parametrien, varauksenkuljettajien liikkuvuus, jäännösvarauksenkuljettajatiheys ja kontaktiresistanssi, selvittämiseksi. Mallille suoritettiin validointi (engl. k-fold crossvalidation).The goal of this master's thesis was to write a literature survey of graphene transistors, and to measure and model the graphene field-effect transistors (GFET) fabricated by Nanotechnology research group at Aalto University. Direct current (DC) and radio frequency (RF) measurements were performed on graphene field-effect transistors to find out the DC and RF properties. Two sets of GFETs were measured, first chip was fabricated with SiC process and the second with CVD process. The SiC GFET impedance levels were too high to measure RF properties. RF-measurements were performed on CVD GFETs. The CVD GFET cut-off frequency was found to be approximately 80 MHz, which is in the same range as the calculated cut-off frequency. MOSFET small-signal model was used for GFETs and the model parameters are presented. The results of the DC measurements were analyzed and the data was fitted according to an existing device resistance model. The curve-fit to total device resistance gives estimations on parameters such as contact resistance, residual charge carrier concentration and conductivity mobility. The model was validated using k-fold cross validation