A Low Power Asynchronous Viterbi Decoder using LEDR Encoding

With the consumer demand for increased content and as a result, increasing high data bandwidth continuing to drive communications systems, coding for error control has become extraordinarily important. One way to improve the Bit Error Rate (BER), while maintaining high data reliability, is to use an error correction technique like the Viterbi algorithm. Originally conceived by Andrew Viterbi as an error-correction scheme for noisy digital communication, the Viterbi algorithm provides an efficient method for Forward Error Correction (FEC) that improves channel reliability. Today, it is used in many digital communications systems in applications as diverse as LTE Physical Downlink Control Channel (PDCCH), CDMA and GSM, digital cellular, dial up modems, satellite, deep-space communications, and 802.11 wireless LANs. Though it is useful for error correction it dissipates large power. A lot many researches were carried out at architectural as well as algorithmic level to optimize the ACS (Add compare and Select) unit and Survival Memory Management in Synchronous Viterbi Decoders. But still there is a problem of power dissipation which requires more technical solutions. Due to requirements of high speed, low power, low weight and long battery life a low power Viterbi decoders has a great demand in the communication field. This paper proposed the method for survivor path storage and decoding as Minimum Transition Hybrid Register Exchange Method along with handshaking protocol as Level Encoded dual rail (LEDR) encoding to make the system asynchronous. The whole system has been designed on algorithmic level and Simulation is done on Xilinx Tool for Asynchronous Viterbi Decoder using MTHREM

Design of Asynchronous Viterbi Decoder for Low Power Applications

In todays digital communication systems, convolutional codes are broadly used in channel coding techniques.The viterbi decoder due to its high performance is commonly used for decoding the convolutional codes. Fast developments in the communication field have created a rising demand for high speed and low power viterbi decoders with long battery life and low weight. Despite the significant progress in the last decade, the problem of power dissapation in the viterbi decoders still remains challenging and requires further technical solutions.In this paper we proposed the methods for survivor path storage and decoding as Register Exchange Method (REM) and Hybrid Register Exchange method (HREM). REM cosumes large power and area, due to huge switching activity.The problem of switching activity of Viterbi decoder can be reduced by combining Traceback and REM and the method called Hybrid Register Exchange Method (HREM). The Viterbi decoder is designed using REM and HREM and simulated on Quartus tool and power is calculated on Power play power analyzer. As the switching activity is reduced in HREM as compared to REM the viterbi decoder achieves reduction in power in HREM as compared with REM .For further reduction in power of viterbi decoder we proposed asynchronous techniques like handshaking protocol. Here we designed the Asynchronous Viterbi decoder by using 2 phase dual rail encoding (LEDR)

High- speed- Low-Power Viterbi Decoder Design

High - speed, low - power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. We propose a pre - computation architecture incorporated with - algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre - computation steps is also given in the paper. Implementation result of a VD for a rate - 3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces th e power consumption

Turbo Decoding and Detection for Wireless Applications

A historical perspective of turbo coding and turbo transceivers inspired by the generic turbo principles is provided, as it evolved from Shannon’s visionary predictions. More specifically, we commence by discussing the turbo principles, which have been shown to be capable of performing close to Shannon’s capacity limit. We continue by reviewing the classic maximum a posteriori probability decoder. These discussions are followed by studying the effect of a range of system parameters in a systematic fashion, in order to gauge their performance ramifications. In the second part of this treatise, we focus our attention on the family of iterative receivers designed for wireless communication systems, which were partly inspired by the invention of turbo codes. More specifically, the family of iteratively detected joint coding and modulation schemes, turbo equalization, concatenated spacetime and channel coding arrangements, as well as multi-user detection and three-stage multimedia systems are highlighted

The design of an asynchronous BCJR/MAP convolutional channel decoder.

The digital design alternative to the everyday synchronous circuit design paradigm is the asynchronous model. Asynchronous circuits are also known as handshaking circuits and they may prove to be a feasible design alternative in the modern digital Very Large Scale Integration (VLSI) design environment. Asynchronous circuits and systems offer the possibility of lower system power requirements, reduced noise, elimination of clock skew and many other benefits. Channel coding is a useful means of eliminating erroneous transmission due to the communication channel\u27s physical limits. Convolutional coding has come to the forefront of channel coding discussions due to the usefulness of turbo codes. The niche market for turbo codes have typically been in satellite communication. The usefulness of turbo codes are now expanding into the next generation of handheld communication products. It is probable that the turbo coding scheme will reside in the next cellular phone one purchases [1]. Turbo coding uses two BCJR decoders in its implementation. The BCJR decoding algorithm was named after its creators Bahl, Cocke, Jelinek, and Raviv (BCJR). The BCJR algorithm is sometimes known as a Maximum Priori Posteriori (MAP) algorithm. This means a very large part of the turbo coding research will encompass the BCJR/MAP decoder and its optimization for size, power and performance. An investigation into the design of a BCJR/MAP convolutional channel decoder will be introduced. This will encompass the use and synthesis of an asynchronous Hardware Definition Language (HDL) called Balsa. The design will be carried through to the gate implementation level. Proper gate level analysis will identify the key metrics that will determine the feasibility of an asynchronous design of that of the everyday clocked paradigm.* *This dissertation is a compound document (contains both a paper copy and a CD as part of the dissertation).Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .P47. Source: Masters Abstracts International, Volume: 43-05, page: 1782. Adviser: Kemal Tepe. Thesis (M.A.Sc.)--University of Windsor (Canada), 2005

Network-Coded Multiple Access

This paper proposes and experimentally demonstrates a first wireless local area network (WLAN) system that jointly exploits physical-layer network coding (PNC) and multiuser decoding (MUD) to boost system throughput. We refer to this multiple access mode as Network-Coded Multiple Access (NCMA). Prior studies on PNC mostly focused on relay networks. NCMA is the first realized multiple access scheme that establishes the usefulness of PNC in a non-relay setting. NCMA allows multiple nodes to transmit simultaneously to the access point (AP) to boost throughput. In the non-relay setting, when two nodes A and B transmit to the AP simultaneously, the AP aims to obtain both packet A and packet B rather than their network-coded packet. An interesting question is whether network coding, specifically PNC which extracts packet (A XOR B), can still be useful in such a setting. We provide an affirmative answer to this question with a novel two-layer decoding approach amenable to real-time implementation. Our USRP prototype indicates that NCMA can boost throughput by 100% in the medium-high SNR regime (>=10dB). We believe further throughput enhancement is possible by allowing more than two users to transmit together