33,073 research outputs found
Modeling and verifying circuits using generalized relative timing
Journal ArticleWe propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not just a relative ordering between events, but also some forms of metric timing constraints. Circuits modeled using generalized relative timing constraints are formally encoded as timed automata. Novel fully symbolic verification algorithms for timed automata are then used to either verify a temporal logic property or to check conformance against an untimed specification. The combination of our new modeling technique with fully symbolic verification methods enables us to verify larger circuits than has been possible with other approaches. We present case studies to demonstrate our approach, including a self-timed circuit used in the integer unit of the Intel® Pentium® 4 processor
Formal Verification of Security Protocol Implementations: A Survey
Automated formal verification of security protocols has been mostly focused on analyzing high-level abstract models which, however, are significantly different from real protocol implementations written in programming languages. Recently, some researchers have started investigating techniques that bring automated formal proofs closer to real implementations. This paper surveys these attempts, focusing on approaches that target the application code that implements protocol logic, rather than the libraries that implement cryptography. According to these approaches, libraries are assumed to correctly implement some models. The aim is to derive formal proofs that, under this assumption, give assurance about the application code that implements the protocol logic. The two main approaches of model extraction and code generation are presented, along with the main techniques adopted for each approac
Formal Modeling of Connectionism using Concurrency Theory, an Approach Based on Automata and Model Checking
This paper illustrates a framework for applying formal methods techniques, which are symbolic in nature, to specifying and verifying neural networks, which are sub-symbolic in nature. The paper describes a communicating automata [Bowman & Gomez, 2006] model of neural networks. We also implement the model using timed automata [Alur & Dill, 1994] and then undertake a verification of these models using the model checker Uppaal [Pettersson, 2000] in order to evaluate the performance of learning algorithms. This paper also presents discussion of a number of broad issues concerning cognitive neuroscience and the debate as to whether symbolic processing or connectionism is a suitable representation of cognitive systems. Additionally, the issue of integrating symbolic techniques, such as formal methods, with complex neural networks is discussed. We then argue that symbolic verifications may give theoretically well-founded ways to evaluate and justify neural learning systems in the field of both theoretical research and real world applications
Compositional Verification for Timed Systems Based on Automatic Invariant Generation
We propose a method for compositional verification to address the state space
explosion problem inherent to model-checking timed systems with a large number
of components. The main challenge is to obtain pertinent global timing
constraints from the timings in the components alone. To this end, we make use
of auxiliary clocks to automatically generate new invariants which capture the
constraints induced by the synchronisations between components. The method has
been implemented in the RTD-Finder tool and successfully experimented on
several benchmarks
The derivation of performance expressions for communication protocols from timed Petri net models
Petri Net models have been extended in a variety of ways and have been used to prove the correctness and evaluate the performance of communication protocols. Several extensions have been proposed to model time. This work uses a form of Timed Petri Nets and presents a technique for symbolically deriving expressions which describe system performance. Unlike past work on performance evaluation of Petri Nets which assumes a priori knowledge of specific time delays, the technique presented here applies to a wide range of time delays so long as the delays satisfy a set of timing constraints. The technique is demonstrated using a simple communication protocol
On Zone-Based Analysis of Duration Probabilistic Automata
We propose an extension of the zone-based algorithmics for analyzing timed
automata to handle systems where timing uncertainty is considered as
probabilistic rather than set-theoretic. We study duration probabilistic
automata (DPA), expressing multiple parallel processes admitting memoryfull
continuously-distributed durations. For this model we develop an extension of
the zone-based forward reachability algorithm whose successor operator is a
density transformer, thus providing a solution to verification and performance
evaluation problems concerning acyclic DPA (or the bounded-horizon behavior of
cyclic DPA).Comment: In Proceedings INFINITY 2010, arXiv:1010.611
Reachability Analysis of Time Basic Petri Nets: a Time Coverage Approach
We introduce a technique for reachability analysis of Time-Basic (TB) Petri
nets, a powerful formalism for real- time systems where time constraints are
expressed as intervals, representing possible transition firing times, whose
bounds are functions of marking's time description. The technique consists of
building a symbolic reachability graph relying on a sort of time coverage, and
overcomes the limitations of the only available analyzer for TB nets, based in
turn on a time-bounded inspection of a (possibly infinite) reachability-tree.
The graph construction algorithm has been automated by a tool-set, briefly
described in the paper together with its main functionality and analysis
capability. A running example is used throughout the paper to sketch the
symbolic graph construction. A use case describing a small real system - that
the running example is an excerpt from - has been employed to benchmark the
technique and the tool-set. The main outcome of this test are also presented in
the paper. Ongoing work, in the perspective of integrating with a
model-checking engine, is shortly discussed.Comment: 8 pages, submitted to conference for publicatio
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