A bibliography on formal methods for system specification, design and validation

Literature on the specification, design, verification, testing, and evaluation of avionics systems was surveyed, providing 655 citations. Journal papers, conference papers, and technical reports are included. Manual and computer-based methods were employed. Keywords used in the online search are listed

Algebraic Specification-Based Performance Analysis or Communication Protocols

Safe and live protocols have been shown to exhibit timing errors. To avoid such errors, timing requirements of protocols should be specified and verified. In this paper, a method for mapping algebraic functional behavior descriptions into corresponding timing behavior descriptions is introduced. Constraints on timing behavior are then expressed and used in specifying and verifying protocol timing requirements. In addition, various protocol performance measures are defined and analyzed. Using the Alternating Bit protocol as an example, an upper bound on the protocol's timeout rate, such that it meets a given timeout requirement, is computed and its maximum throughput and mean transfer time are analyzed

A Methodology for Specification-Based Performance Analysis of Protocols

The designer of communication protocols has to formulate rules to govern the communications between processes that are distributed; share common resources concurrently and asynchronously; communicate through unreliable channels that incur random delays; and behave in a time-dependent fashion. The first step is to formally specify the behavior of each of the communicating processes in the protocol. The protocol designer then has to analyze their concurrent behavior to ensure that it satisfies given functional requirements. He also has to analyze their timing behavior to ensure that is meets given timing requirements. The author addresses the specification and analysis of timing requirements and performance measures of protocols

Development Tools for Communication Protocols: An Overview

This paper presents an overview of commonly used protocol development tools falling under two categories: construction tools and validation tools. Construction tools are used to develop protocols from specifications to working systems. They include tools for specification synthesis and implementation. Validation tools are used to analyze protocols behavior. They include tools for formal verification, performance evaluation and testing. For each tool, we examine the key underlying issues, outline the main approaches, and illustrate its application to a send-and wait protocol

An Automated Performance Analysis of a Two Phase Locking Protocol

ANALYST, an interactive protocol performance analyzer, is used to analyze the performance of a two phase locking protocol. ANALYST implements a specification-based methodology for performance analysis of protocols which extracts from an algebraic specification of a protocol a model of its timing behavior. Any timing requirement or performance measure that can be formally specified in terms of attributes of this timing behavior can be thus analyzed. An algebraic specification of a two phase locking protocol that uses time-out for deadlock detection is provided. Two timing requirements necessary for its efficient performance are specified and analyzed yielding optimal settings of protocol parameters (such as timeout rate). Additionally, the mean response time and probability of deadlock of the protocol are specified and analyzed. This, to the best knowledge of the authors, is the first automated, analytic performance analysis of such a high-level protocol

Space power distribution system technology. Volume 2: Autonomous power management

Electrical power subsystem requirements, power management system functional requirements, algorithms, power management subsystem, hardware development, and trade studies and analyses are discussed

Specification and implementation of computer network protocols

A reliable and effective computer network can only be achieved by adopting efficient and error-free communication protocols. Therefore, the protocol designer should produce an unambiguous specification meeting these requirements. Techniques for producing protocol specifications have been the subject of intense interest over the last few years. This is partly due to the advent of an international standard for networking. A variety of methods have been employed, some of which are described in detail in this thesis. [Continues.

Génération de séquences de test pour l'accélération d'assertions

Avec la complexité croissante des systèmes sur puce, le processus de vérification devient une tâche de plus en plus cruciale à tous les niveaux du cycle de conception, et monopolise une part importante du temps de développement. Dans ce contexte, l'assertion-based verification (ABV) a considérablement gagné en popularité ces dernières années. Il s'agit de spécifier le comportement attendu du système par l'intermédiaire de propriétés logico-temporelles, et de vérifier ces propriétés par des méthodes semi-formelles ou formelles. Des langages de spécification comme PSL ou SVA (standards IEEE) sont couramment utilisés pour exprimer ces propriétés. Des techniques de vérification statiques (model checking) ou dynamiques (validation en cours de simulation) peuvent être mises en œuvre. Nous nous plaçons dans le contexte de la vérification dynamique. A partir d'assertions exprimées en PSL ou SVA, des descriptions VHDL ou Verilog synthétisables de moniteurs matériels de surveillance peuvent être produites (outil Horus). Ces composants peuvent être utilisés pendant la conception (en simulation et/ou émulation pour le débug et la validation de circuits), ou comme composants embarqués, pour la surveillance du comportement de systèmes critiques. Pour l'analyse en phase de conception, que ce soit en simulation ou en émulation, le problème de la génération des séquences de test se pose. En effet, des séquences de test générées aléatoirement peuvent conduire à un faible taux de couverture des conditions d'activation des moniteurs et, de ce fait, peuvent être peu révélatrices de la satisfaction des assertions. Les méthodes de génération de séquences de test sous contraintes n'apportent pas de réelle solution car les contraintes ne peuvent pas être liées à des conditions temporelles. De nouvelles méthodes doivent être spécifiées et implémentées, c'est ce que nous nous proposons d'étudier dans cette thèse.With the increasing complexity of SoC, the verification process becomes a task more crucial at all levels of the design cycle, and monopolize a large share of development time. In this context, the assertion-based verification (ABV) has gained considerable popularity in recent years. This is to specify the behavior of the system through logico-temporal properties and check these properties by semiformal or formal methods. Specification languages such as PSL or SVA (IEEE) are commonly used to express these properties. Static verification techniques (model checking) or dynamic (during simulation) can be implemented. We are placed in the context of dynamic verification. Our assertions are expressed in PSL or SVA, and synthesizable descriptions VHDL or Verilog hardware surveillance monitors can be produced (Horus tool). These components can be used for design (simulation and/or emulation for circuit debug and validation) or as embedded components for monitoring the behavior of critical systems. For analysis in the design phase, either in simulation or emulation, the problem of generating test sequences arises. In effect, sequences of randomly generated test can lead to a low coverage conditions of activation monitors and, therefore, may be indicative of little satisfaction assertions. The methods of generation of test sequences under constraints do not provide real solution because the constraints can not be linked to temporal conditions. New methods must be specified and implemented, this's what we propose to study in this thesis.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF