56+ Gb/s serial transmission using duo-binary signaling

In this paper we present duobinary signaling as an alternative for signaling schemes like PAM4 and Ensemble NRZ that are currently being considered as ways to achieve data rates of 56 Gb/s over copper. At the system level, the design includes a custom transceiver ASIC. The transmitter is capable of equalizing 56 Gb/s non-return to zero (NRZ) signals into a duobinary response at the output of the channel. The receiver includes dedicated hardware to decode the duobinary signal. This transceiver is used to demonstrate error-free transmission for different PCB channel lengths including a state-of-the-art Megtron 6 backplane demonstrator

대역폭 증대 기술을 이용한 전력 효율적 고속 송신 시스템 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.The high-speed interconnect at the datacenter is being more crucial as 400 Gb Ethernet standards are developed. At the high data rate, channel loss re-quires bandwidth extension techniques for transmitters, even for short-reach channels. On the other hand, as the importance of east-to-west connection is rising, the data center architectures are switching to spine-leaf from traditional ones. In this trend, the number of short-reach optical interconnect is expected to be dominant. The vertical-cavity surface-emitting laser (VCSEL) is a com-monly used optical modulator for short-reach interconnect. However, since VCSEL has low bandwidth and nonlinearity, the optical transmitter also needs bandwidth-increasing techniques. Additionally, the power consumption of data centers reaches a point of concern to affect climate change. Therefore, this the-sis focuses on high-speed, power-efficient transmitters for data center applica-tions. Before the presenting circuit design, bandwidth extension techniques such as fractionally-spaced feed-forward equalizer (FFE), on-chip transmission line, inductive peaking, and T-coil are mathematically analyzed for their effec-tiveness. For the first chip, a power and area-efficient pulse-amplitude modulation 4 (PAM-4) transmitter using 3-tap FFE based on a slow-wave transmission line is presented. A passive delay line is adopted for generating an equalizer tap to overcome the high clocking power consumption. The transmission line achieves a high slow-wave factor of 15 with double floating metal shields around the differential coplanar waveguide. The transmitter includes 4:1 multi-plexers (MUXs) and a quadrature clock generator for high-speed data genera-tion in a quarter-rate system. The 4:1 MUX utilizes a 2-UI pulse generator, and the input configuration is determined by qualitative analysis. The chip is fabri-cated in 65 nm CMOS technology and occupies an area of 0.151 mm2. The proposed transmitter system exhibits an energy efficiency of 3.03 pJ/b at the data rate of 48 Gb/s with PAM-4 signaling. The second chip presents a power-efficient PAM-4 VCSEL transmitter using 3-tap FFE and negative-k T-coil. The phase interpolators (PIs) generate frac-tionally-spaced FFE tap and correct quadrature phase error. The PAM-4 com-bining 8:1 MUX is proposed rather than combining at output driver with double 4:1 MUXs to reduce serializing power consumption. T-coils at the internal and output node increase the bandwidth and remove inter-symbol interference (ISI). The negative-k T-coil at the output network increases the bandwidth 1.61 times than without T-coil. The VCSEL driver is placed on the high VSS domain for anode driving and power reduction. The chip is fabricated in 40 nm CMOS technology. The proposed VCSEL transmitter operates up to 48 Gb/s NRZ and 64 Gb/s PAM-4 with the power efficiency of 3.03 pJ/b and 2.09 pJ/b, respec-tively.400Gb 이더넷 표준이 개발됨에 따라 데이터 센터의 고속 상호 연결이 더욱 중요해지고 있다. 높은 데이터 속도에서의 채널 손실에 의해 단거리 채널의 경우에도 송신기에 대한 대역폭 확장 기술이 필요하다. 한편, 데이터 센터 내 동-서 연결의 중요성이 높아지면서 데이터 센터 아키텍처가 기존의 아키텍처에서 스파인-리프로 전환되고 있다. 이러한 추세에서 단거리 광학 인터커넥트의 수가 점차 우세해질 것으로 예상된다. 수직 캐비티 표면 방출 레이저(VCSEL)는 일반적으로 단거리 상호 연결을 위해 사용되는 광학 모듈레이터이다. VCSEL은 낮은 대역폭과 비선형성을 가지고 있기 때문에, 광 송신기도 대역폭 증가 기술을 필요로 한다. 또한, 데이터 센터의 전력 소비는 기후 변화에 영향을 미칠 수 있는 우려 지점에 도달했다. 따라서, 본 논문은 데이터 센터 응용을 위한 고속 전력 효율적인 송신기에 초점을 맞추고 있다. 회로 설계를 제시하기 전에, 부분 간격 피드-포워드 이퀄라이저 (FFE), 온칩 전송선로, 인덕터, T-코일과 같은 대역폭 확장 기술을 수학적으로 분석한다. 첫 번째 칩은 저속파 전송선로를 기반으로 한 3-탭 FFE를 사용하는 전력 및 면적 효율적인 펄스-진폭-변조 4(PAM-4) 송신기를 제시한다. 높은 클럭 전력 소비를 극복하기 위해 이퀄라이저 탭 생성을 위해 수동소자 지연 라인을 채택했다. 전송 라인은 차동 동일평면도파관 주위에 이중 플로팅 금속 차폐를 사용하여 15의 높은 전달속도 감쇠를 달성한다. 송신기에는 4:1 멀티플렉서(MUX)와 4-위상 클럭 생성기가 포함되어 있다. 4:1 MUX는 2-UI 펄스 발생기를 사용하며, 정성 분석에 의해 입력 구성이 결정된다. 이 칩은 65 nm CMOS 기술로 제작되었으며 0.151 mm2의 면적을 차지한다. 제안된 송신기 시스템은 PAM-4 신호와 함께 48 Gb/s의 데이터 속도에서 3.03 pJ/b의 에너지 효율을 보여준다. 두 번째 칩에서는 3-탭 FFE 및 역회전 T-코일을 사용하는 전력 효율적인 PAM-4 VCSEL 송신기를 제시한다. 위상 보간기(PI)는 부분 간격 FFE 탭을 생성하고 4-위상 클럭 오류를 수정하는 데 사용된다. 직렬화 전력 소비를 줄이기 위해 출력 드라이버에서 MSB와 LSB를 두 개의 4:1 MUX를 통해 결합하는 대신 8:1 MUX를 통해 PAM-4로 결합하는 회로가 제안된다. 내부 및 출력 노드에서 T-코일은 대역폭을 증가시키고 기호 간 간섭(ISI)을 제거한다. 출력 네트워크에서 역회전 T-코일은 T-코일이 없는 경우보다 대역폭을 1.61배 증가시킨다. VCSEL 드라이버는 양극 구동 및 전력 감소를 위해 높은 VSS 도메인에 배치된다. 이 칩은 40 nm CMOS 기술로 제작되었다. 제안된 VCSEL 송신기는 각각 3.03pJ/b와 2.09pJ/b의 전력 효율로 최대 48Gb/s NRZ와 64Gb/s PAM-4까지 작동한다.ABSTRACT I CONTENTS III LIST OF FIGURES V LIST OF TABLES IX CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 BACKGROUND OF HIGH-SPEED INTERFACE 6 2.1 OVERVIEW 6 2.2 BASIS OF DATA CENTER ARCHITECTURE 9 2.3 SHORT-REACH INTERFACE STANDARDS 12 2.4 ANALYSES OF BANDWIDTH EXTENSION TECHNIQUES 16 2.4.1 FRACTIONALLY-SPACED FFE 16 2.4.2 TRANSMISSION LINE 21 2.4.3 INDUCTOR 24 2.4.4 T-COIL 33 CHAPTER 3 DESIGN OF 48 GB/S PAM-4 ELECTRICAL TRANSMITTER IN 65 NM CMOS 43 3.1 OVERVIEW 43 3.2 FFE BASED ON DOUBLE-SHIELDED COPLANAR WAVEGUIDE 46 3.2.1 BASIC CONCEPT 46 3.2.2 PROPOSED DOUBLE-SHIELDED COPLANAR WAVEGUIDE 47 3.3 DESIGN CONSIDERATION ON 4:1 MUX 50 3.4 PROPOSED PAM-4 ELECTRICAL TRANSMITTER 53 3.5 MEASUREMENT 57 CHAPTER 4 DESIGN OF 64 GB/S PAM-4 OPTICAL TRANSMITTER IN 40 NM CMOS 64 4.1 OVERVIEW 64 4.2 DESIGN CONSIDERATION OF OPTICAL TRANSMITTER 66 4.3 PROPOSED PAM-4 VCSEL TRANSMITTER 69 4.4 MEASUREMENT 82 CHAPTER 5 CONCLUSIONS 88 BIBLIOGRAPHY 90 초 록 101박

High-speed equalization and transmission in electrical interconnections

The relentless growth of data traffic and increasing digital signal processing capabilities of integrated circuits (IC) are demanding ever faster chip-to-chip / chip-to-module serial electrical interconnects. As data rates increase, the signal quality after transmission over printed circuit board (PCB) interconnections is severely impaired. Frequency-dependent loss and crosstalk noise lead to a reduced eye opening, a reduced signal-to-noise ratio and an increased inter-symbol interference (ISI). This, in turn, requires the use of improved signal processing or PCB materials, in order to overcome the bandwidth (BW) limitations and to improve signal integrity. By applying an optimal combination of equalizer and receiver electronics together with BW-efficient modulation schemes, the transmission rate over serial electrical interconnections can be pushed further. At the start of this research, most industrial backplane connectors, meeting the IEEE and OIF specifications such as manufactured by e.g. FCI or TE connectivity, had operational capabilities of up to 25 Gb/s. This research was mainly performed under the IWT ShortTrack project. The goal of this research was to increase the transmission speed over electrical backplanes up to 100 Gb/s per channel for next-generation telecom systems and data centers. This requirement greatly surpassed the state-ofthe-art reported in previous publications, considering e.g. 25 Gb/s duobinary and 42.8 Gb/s PAM-4 transmission over a low-loss Megtron 6 electrical backplane using off-line processing. The successful implementation of the integrated transmitter (TX) and receiver (RX) (1) , clearly shows the feasibility of single lane interconnections beyond 80 Gb/s and opens the potential of realizing industrial 100 Gb/s links using a recent IC technology process. Besides the advancement of the state-of-the-art in the field of high-speed transceivers and backplane transmission systems, which led to several academic publications, the output of this work also attracts a lot of attention from the industry, showing the potential to commercialize the developed chipset and technologies used in this research for various applications: not only in high-speed electrical transmission links, but also in high-speed opto-electronic communications such as access, active optical cables and optical backplanes. In this dissertation, the background of this research, an overview of this work and the thesis organization are illustrated in Chapter 1. In Chapter 2, a system level analysis is presented, showing that the channel losses are limiting the transmission speed over backplanes. In order to enhance the serial data rate over backplanes and to eliminate the signal degradation, several technologies are discussed, such as signal equalization and modulation techniques. First, a prototype backplane channel, from project partner FCI, implemented with improved backplane connectors is characterized. Second, an integrated transversal filter as a feed-forward equalizer (FFE) is selected to perform the signal equalization, based on a comprehensive consideration of the backplane channel performance, equalization capabilities, implementation complexity and overall power consumption. NRZ, duobinary and PAM-4 are the three most common modulation schemes for ultra-high speed electrical backplane communication. After a system-level simulation and comparison, the duobinary format is selected due to its high BW efficiency and reasonable circuit complexity. Last, different IC technology processes are compared and the ST microelectronics BiCMOS9MW process (featuring a fT value of over 200 GHz) is selected, based on a trade-off between speed and chip cost. Meanwhile it also has a benefit for providing an integrated microstrip model, which is utilized for the delay elements of the FFE. Chapter 3 illustrates the chip design of the high-speed backplane TX, consisting of a multiplexer (MUX) and a 5-tap FFE. The 4:1 MUX combines four lower rate streams into a high-speed differential NRZ signal up to 100 Gb/s as the FFE input. The 5-tap FFE is implemented with a novel topology for improved testability, such that the FFE performance can be individually characterized, in both frequency- and time-domain, which also helps to perform the coefficient optimization of the FFE. Different configurations for the gain cell in the FFE are compared. The gilbert configuration shows most advantages, in both a good high-frequency performance and an easy way to implement positive / negative amplification. The total chip, including the MUX and the FFE, consumes 750mW from a 2.5V supply and occupies an area of 4.4mm × 1.4 mm. In Chapter 4, the TX chip is demonstrated up to 84 Gb/s. First, the FFE performance is characterized in the frequency domain, showing that the FFE is able to work up to 84 Gb/s using duobinary formats. Second, the combination of the MUX and the FFE is tested. The equalized TX outputs are captured after different channels, for both NRZ and duobinary signaling at speeds from 64 Gb/s to 84 Gb/s. Then, by applying the duobinary RX 2, a serial electrical transmission link is demonstrated across a pair of 10 cm coax cables and across a 5 cm FX-2 differential stripline. The 5-tap FFE compensates a total loss between the TX and the RX chips of about 13.5 dB at the Nyquist frequency, while the RX receives the equalized signal and decodes the duobinary signal to 4 quarter rate NRZ streams. This shows a chip-to-chip data link with a bit error rate (BER) lower than 10−11. Last, the electrical data transmission between the TX and the RX over two commercial backplanes is demonstrated. An error-free, serial duobinary transmission across a commercial Megtron 6, 11.5 inch backplane is demonstrated at 48 Gb/s, which indicates that duobinary outperforms NRZ for attaining higher speed or longer reach backplane applications. Later on, using an ExaMAX® backplane demonstrator, duobinary transmission performance is verified and the maximum allowed channel loss at 40 Gb/s transmission is explored. The eye diagram and BER measurements over a backplane channel up to 26.25 inch are performed. The results show that at 40 Gb/s, a total channel loss up to 37 dB at the Nyquist frequency allows for error-free duobinary transmission, while a total channel loss of 42 dB was overcome with a BER below 10−8. An overview of the conclusions is summarized in Chapter 5, along with some suggestions for further research in this field. (1) The duobinary receiver was developed by my colleague Timothy De Keulenaer, as described in his PhD dissertation. (2) Described in the PhD dissertation of Timothy De Keulenaer

Modeling and Design of Architectures for High-Speed ADC-Based Serial Links

There is an ongoing dramatic rise in the volume of internet traffic. Standards such as 56Gb/s OIF very short reach (VSR), medium reach (MR) and long reach (LR) standards for chip to chip communication over channels with up to 10dB, 20dB and 30dB insertion loss at the PAM 4 Nyquist frequency, respectively, are being adopted. These standards call for the spectrally efficient PAM-4 signaling over NRZ signaling. PAM-4 signaling offers challenges such as a reduced SNR at the receiver, susceptibility to nonlinearities and increased sensitivity to residual ISI. Equalization provided by traditional mixed signal architectures can be insufficient to achieve the target BER requirements for very long reach channels. ADC-based receiver architectures for PAM-4 links take advantage of the more powerful equalization techniques, which lend themselves to easier and robust digital implementations, to extend the amount of insertion loss that the receiver can handle. However, ADC-based receivers can consume more power compared to mixed-signal implementations. Techniques that model the receiver performance to understand the various system trade-offs are necessary. This research presents a fast and accurate hybrid modeling framework to efficiently investigate system trade-offs for an ADC-based receiver. The key contribution being the addition of ADC related non-idealities such as quantization noise in the presence of integral and differential nonlinearities, and time-interleaving mismatch errors such as gain mismatch, bandwidth mismatch, offset mismatch and sampling skew. The research also presents a 52Gb/s ADC-based PAM-4 receiver prototype employing a 32-way time-interleaved, 2-bit/stage, 6-bit SAR ADC and a DSP with a 12-tap FFE and a 2-tap DFE. A new DFE architecture that reduces the complexity of a PAM-4 DFE to that of an NRZ DFE while simultaneously nearly doubling the maximum achievable data rate is presented. The receiver architecture also includes an analog front-end (AFE) consisting of a programmable two stage CTLE. A digital baud-rate CDR’s utilizing a Mueller-Muller phase detector sets the sampling phase. Measurement results show that for 32Gb/s operation a BER < 10⁻⁹ is achieved for a 30dB loss channel while for 52 Gb/s operation achieves a BER < 10⁻⁶ for a 31dB loss channel with a power efficiency of 8.06pj/bit

Design of Energy-Efficient Equalization and Data Encoding/Decoding Techniques for Wireline Communication Systems

Ever increasing global internet data traffic has driven up the demand for cutting-edge high-speed wireline communication systems including SerDes PHY for various interfaces, interconnects, data centers servers and switches in optical systems. Operating wireline communications at higher data rates leads to signals suffering from greater channel loss and exponential increase in power consumption, mainly caused by a heavier amount of required equalization. In this dissertation, two distinct methodologies for designing SerDes transceivers are presented: 1) a pulse width modulated (PWM) time-domain feed forward equalizer (FFE) and linearity improvement technique for higher-order pulse amplitude modulation (PAM) including PAM-8, and 2) an inter-symbol interference (ISI)-resilient data encoding and decoding technique with Dicode encoding and error correction logic for low-bandwidth wireline channels, as an alternative strategy for communicating in an energy-efficient way on bandwidth-limited wireline channels without using conventional equalizers or filters. The first topic is a PAM-8 wireline transceiver with receiver-side pulse-width-modulated (PWM) or time-domain based feed forward equalization (FFE) technique. The receiver converts voltage-modulated signals or PAM signals to PWM signals and processes them using inverter based delay elements having rail to rail voltage swing. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity on the receiver. The proposed PAM-8 transceiver can operate from 12.0 Gb/s to 39.6 Gb/s and compensates 14 dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65 nm CMOS. The second topic is an alternative strategy for communicating on bandwidth-limited wireline channels without using conventional equalizers or filters (FFE, DFE, and CTLE): Inter-symbol interference (ISI) resilient Dicode encoding and error correction for low-bandwidth wireline channels. The key observation is that Dicode-encoded data have no consecutive 1s or -1s. With this known information, the error correction logic at the receiver can correct multi-bit errors due to ISI. Implemented in 65 nm CMOS, the proposed digital encoding and decoding approach can achieve BER less than 10−12 while communicating on a channel with an insertion loss of 24.2 dB and 21.4 dB with 2.56 pJ/bit and 2.66 pJ/bit efficiency while operating at 13.6 Gb/s and 16 Gb/s, respectively