1,203 research outputs found

    Design of a High-Performance High-Pass Generalized Integrator Based Single-Phase PLL

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    Grid-interactive power converters are normally synchronized to the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations and dc offsets in single-phase systems. In this paper, a single-phase PLL is presented to mitigate the effects of these non-idealities. This PLL is based on the popular second order generalized integrator (SOGI) structure. The SOGI structure is modified to eliminate of the effects of input dc offsets. The resulting SOGI structure has a high-pass filtering property. Hence, this PLL is termed as high-pass generalized integrator based PLL (HGI-PLL). It has fixed parameters which reduces the implementation complexity and aids in the implementation in low-end digital controllers. The HGI-PLL is shown to have least resource utilization among the SOGI based PLLs with dc cancelling capability. Systematic design methods are evolved leading to the design that limits the unit vector THD to within 1% for given non-ideal input conditions in terms of frequency deviation and harmonic distortion. The proposed designs achieve the fastest transient response. The performance of this PLL has been verified experimentally. The results are found to agree with the theoretical prediction.Comment: 22 pages, 13 figures and 2 table

    Adaptive Vectorial Filter for Grid Synchronization of Power Converters Under Unbalanced and/or Distorted Grid Conditions

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    This paper presents a new synchronization scheme for detecting multiple positive-/negative-sequence frequency harmonics in three-phase systems for grid-connected power converters. The proposed technique is called MAVF-FLL because it is based on the use of multiple adaptive vectorial filters (AVFs) working together inside a harmonic decoupling network, resting on a frequency-locked loop (FLL) which makes the system frequency adaptive. The method uses the vectorial properties of the three-phase input signal in the αβ reference frame in order to obtain the different harmonic components. The MAVF-FLL is fully designed and analyzed, addressing the tuning procedure in order to obtain the desired and predefined performance. The proposed algorithm is evaluated by both simulation and experimental results, demonstrating its ability to perform as required for detecting different harmonic components under a highly unbalanced and distorted input grid voltage

    Exploitation of Digital Filters to Advance the Single-Phase T/4 Delay PLL System

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    With the development of digital signal processing technologies, control and monitoring of power electronics conversion systems have been evolving to become fully digital. As the basic element in the design and analysis phases of digital controllers or filters, a number of unit delays (z-1) have been employed, e.g., in a cascaded structure. Practically, the number of unit delays is designed as an integer, which is related to the sampling frequency as well as the ac signal fundamental frequency (e.g., 50 Hz). More common, the sampling frequency is fixed during operation for simplicity and design. Hence, any disturbance in the ac signal will violate this design rule and it can become a major challenge for digital controllers. To deal with the above issue, this paper first exploits a virtual unit delay (zv-1) to emulate the variable sampling behavior in practical digital signal processors with a fixed sampling rate. This exploitation is demonstrated on a T/4 Delay Phase Locked Loop (PLL) system for a single-phase grid-connected inverter. The T/4 Delay PLL requires to cascade 50 unit delays when implemented (for a 50-Hz system with 10 kHz sampling frequency). Furthermore, digital frequency adaptive comb filters are adopted to enhance the performance of the T/4 Delay PLL when the grid suffers from harmonics. Experimental results have confirmed the effectiveness of the digital filters for advanced control systems

    Three-phase phase-locked loop synchronization algorithms for grid-connected renewable energy systems:A review

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    The increasing penetration of distributed renewable energy sources (RES) requires appropriate control techniques in order to remain interconnected and contribute in a proper way to the overall grid stability, whenever disturbances occur. In addition, the disconnection of RES due to synchronization problems must be avoided as this may result in penalties and loss of energy generation to RES operators. The control of RES mainly depends on the synchronization algorithm, which should be fast and accurately detect the grid voltage status (e.g., phase, amplitude, and frequency). Typically, phase-locked loop (PLL) synchronization techniques are used for the grid voltage monitoring. The design and performance of PLL directly affect the dynamics of the RES grid side converter (GSC). This paper presents the characteristics, design guidelines and features of advanced state-of-the-art PLL-based synchronization algorithms under normal, abnormal and harmonically-distorted grid conditions. Experimental tests on the selected PLL methods under different grid conditions are presented, followed by a comparative benchmarking and selection guide. Finally, corresponding PLL tuning procedures are discussed.This work was supported by the supported by the Research Promotion Foundation (RPF) of Cyprus under Project KOINA/SOLAR-ERA.NET/1215/06

    Variable-Frequency Grid-Sequence Detector Based on a Quasi-Ideal Low-Pass Filter Stage and a Phase-Locked Loop

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    This paper proposes a filtered-sequence phase-locked loop (FSPLL) structure for detection of the positive sequence in three-phase systems. The structure includes the use of the Park transformation and moving average filters (MAF). Performance of the MAF is mathematically analyzed and represented in Bode diagrams. The analysis allows a proper selection of the window width of the optimal filter for its application in the dq transformed variables. The proposed detector structure allows fast detection of the grid voltage positive sequence (within one grid voltage cycle). The MAF eliminates completely any oscillation multiple of the frequency for which it is designed; thus, this algorithm is not affected by the presence of imbalances or harmonics in the electrical grid. Furthermore, the PLL includes a simple-frequency detector that makes frequency adaptive the frequency depending blocks. This guarantees the proper operation of the FSPLL under large frequency changes. The performance of the entire PLL-based detector is verified through simulation and experiment. It shows veryPeer ReviewedPostprint (published version

    On the Enhancement of Generalized Integrator-based Adaptive Filter Dynamic Tuning Range

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    Performance of direct power controlled grid-connected voltage source converters

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    PhD ThesisIn this thesis the performance of direct power controlled grid-connected voltage source converters (VSCs) is investigated. Of particular interest is the stability of the controller with the third-order LCL filter employed as the grid filter, effect of grid impedance variations and grid voltage distortion, and current limitation during voltage dips. The control scheme implemented is virtual-flux direct power control with space vector modulation (VF-DPC-SVM). By mathematical modelling and stability analysis, it is found that the closed-loop power control system is stable for all values of proportional gain when the current sensors are on the inverter side of the LCL filter. The inverter current together with the estimated grid virtual-flux is used to estimate the active power and the reactive power. The difference between the estimated reactive power and the reactive power on the grid side is compensated for, using a new reactive power error compensation scheme based on the estimated capacitor current. The control system is found to be robust to changes in grid inductance, and remains stable for a range of grid inductance values, and controller proportional gain. It is demonstrated in simulation and experimentally that the total harmonic distortion (THD) of the current injected by the VSC is less than the limit of 5 %, set by standards, for all different values of grid inductance and proportional gain. This is true even in the presence of significant grid voltage distortion. To control the VSC during voltage dips without damaging the semiconductor devices, a new current limiting algorithm is proposed and implemented. The positive-sequence component of the virtual-flux is used for synchronization and power estimation to achieve balanced, undistorted currents during unsymmetrical voltage dips. Experimental results show that the current achieved during unsymmetrical voltage dips is balanced and has a THD of less than 3 %.Commonwealth Scholarship and Fellowship Plan, Copperbelt Universit

    A Novel Open-Loop Frequency Estimation Method for Single-Phase Grid Synchronization under Distorted Conditions

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    © 2013 IEEE. In this paper, a new open-loop architecture with good dynamic performance and strong harmonic rejection capability is proposed for single-phase grid synchronization under distorted conditions. Different from previous single-phase grid synchronization algorithms based on the phase-locked loop technique, the proposed method is to estimate the frequency and phase angle of the grid voltage in an open-loop manner so that fast dynamic response and enhanced system stability can be achieved. First, an open-loop frequency estimation algorithm is introduced under ideal grid condition. Then, it is extended to distorted grid voltages through the combination of the developed frequency estimation unit and a prefiltering stage consisting of a second-order low-pass filter and a cascaded delayed signal cancellation (DSC) module. In addition, a transient process smoothing unit is designed to achieve smooth frequency transients in cases where the grid voltage experiences fast and large changes. The working principle of the new frequency estimation algorithm and the developed single-phase grid synchronization approach is given in detail, together with some simulation and experiment results for verifying their performance

    Quasi Type-1 PLL With Tunable Phase Detector for Unbalanced and Distorted Three-Phase Grid

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