Intelligent approaches to VLSI routing

Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As a result, conventional approaches, which have been successfully used to handle relatively small-size routing problems, are not suitable to be used in tackling large-size routing problems because they lead to \u27combinatorial explosion\u27 in search space. Hence, there is a need for exploring more efficient routing approaches to be incorporated into today\u27s VLSI routing system. This thesis strives to use intelligent approaches, including symbolic intelligence and computational intelligence, to solve three VLSI routing problems: Three-Dimensional (3-D) Shortest Path Connection, Switchbox Routing and Constrained Via Minimization. The 3-D shortest path connection is a fundamental problem in VLSI routing. It aims to connect two terminals of a net that are distributed in a 3-D routing space subject to technological constraints and performance requirements. Aiming at increasing computation speed and decreasing storage space requirements, we present a new A* algorithm for the 3-D shortest path connection problem in this thesis. This new A*algorithm uses an economical representation and adopts a novel back- trace technique. It is shown that this algorithm can guarantee to find a path if one exists and the path found is the shortest one. In addition, its computation speed is fast, especially when routed nets are spare. The computational complexities of this A* algorithm at the best case and the worst case are O(Ɩ) and 0(Ɩ3), respectively, where Ɩ is the shortest path length between the two terminals. Most importantly, this A\u27 algorithm is superior to other shortest path connection algorithms as it is economical in terms of storage space requirement, i.e., 1 bit/grid. The switchbox routing problem aims to connect terminals at regular intervals on the four sides of a rectangle routing region. From a computational point of view, the problem is NP-hard. Furthermore, it is extremely complicated and as the consequence no existing algorithm can guarantee to find a solution even if one exists no matter how high the complexity of the algorithm is. Previous approaches to the switch box routing problem can be divided into algorithmic approaches and knowledge-based approaches. The algorithmic approaches are efficient in computational time, but they are unsucessful at achieving high routing completion rate, especially for some dense and complicated switchbox routing problems. On the other hand, the knowledge-based approaches can achieve high routing completion rate, but they are not efficient in computation speed. In this thesis we present a hybrid approach to the switchbox routing problem. This hybrid approach is based on a new knowledge-based routing technique, namely synchronized routing, and combines some efficient algorithmic routing techniques. Experimental results show it can achieve the high routing completion rate of the knowledge-based approaches and the high efficiency of the algorithmic approaches. The constrained via minimization is an important optimization problem in VLSI routing. Its objective is to minimize the number of vias introduced in VLSI routing. From computational perspective, the constrained via minimization is NP-complete. Although for a special case where the number of wire segments splits at a via candidate is not more than three, elegant theoretical results have been obtained. For a general case in which there exist more than three wire segment splits at a via candidate few approaches have been proposed, and those approaches are only suitable for tackling some particular routing styles and are difficult or impossible to adjust to meet practical requirements. In this thesis we propose a new graph-theoretic model, namely switching graph model, for the constrained via minimization problem. The switching graph model can represent both grid-based and grid less routing problems, and allows arbitrary wire segments split at a via candidate. Then on the basis of the model, we present the first genetic algorithm for the constrained via minimization problem. This genetic algorithm can tackle various kinds of routing styles and be configured to meet practical constraints. Experimental results show that the genetic algorithm can find the optimal solutions for most cases in reasonable time

Design automation and analysis of three-dimensional integrated circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 165-176).This dissertation concerns the design of circuits and systems for an emerging technology known as three-dimensional integration. By stacking individual components, dice, or whole wafers using a high-density electromechanical interconnect, three-dimensional integration can achieve scalability and performance exceeding that of conventional fabrication technologies. There are two main contributions of this thesis. The first is a computer-aided design flow for the digital components of a three-dimensional integrated circuit (3-D IC). This flow primarily consists of two software tools: PR3D, a placement and routing tool for custom 3-D ICs based on standard cells, and 3-D Magic, a tool for designing, editing, and testing physical layout characteristics of 3-D ICs. The second contribution of this thesis is a performance analysis of the digital components of 3-D ICs. We use the above tools to determine the extent to which 3-D integration can improve timing, energy, and thermal performance. In doing so, we verify the estimates of stochastic computational models for 3-D IC interconnects and find that the models predict the optimal 3-D wire length to within 20% accuracy. We expand upon this analysis by examining how 3-D technology factors affect the optimal wire length that can be obtained. Our ultimate analysis extends this work by directly considering timing and energy in 3-D ICs. In all cases we find that significant performance improvements are possible. In contrast, thermal performance is expected to worsen with the use of 3-D integration. We examine precisely how thermal behavior scales in 3-D integration and determine quantitatively how the temperature may be controlled during the circuit placement process. We also show how advanced packaging(cont.) technologies may be leveraged to maintain acceptable die temperatures in 3-D ICs. Finally, we explore two issues for the future of 3-D integration. We determine how technology scaling impacts the effect of 3-D integration on circuit performance. We also consider how to improve the performance of digital components in a mixed-signal 3-D integrated circuit. We conclude with a look towards future 3-D IC design tools.by Shamik Das.Ph.D

Modeling single-phase flow and solute transport across scales

textFlow and transport phenomena in the subsurface often span a wide range of length (nanometers to kilometers) and time (nanoseconds to years) scales, and frequently arise in applications of CO₂ sequestration, pollutant transport, and near-well acid stimulation. Reliable field-scale predictions depend on our predictive capacity at each individual scale as well as our ability to accurately propagate information across scales. Pore-scale modeling (coupled with experiments) has assumed an important role in improving our fundamental understanding at the small scale, and is frequently used to inform/guide modeling efforts at larger scales. Among the various methods, there often exists a trade-off between computational efficiency/simplicity and accuracy. While high-resolution methods are very accurate, they are computationally limited to relatively small domains. Since macroscopic properties of a porous medium are statistically representative only when sample sizes are sufficiently large, simple and efficient pore-scale methods are more attractive. In this work, two Eulerian pore-network models for simulating single-phase flow and solute transport are developed. The models focus on capturing two key pore-level mechanisms: a) partial mixing within pores (large void volumes), and b) shear dispersion within throats (narrow constrictions connecting the pores), which are shown to have a substantial impact on transverse and longitudinal dispersion coefficients at the macro scale. The models are verified with high-resolution pore-scale methods and validated against micromodel experiments as well as experimental data from the literature. Studies regarding the significance of different pore-level mixing assumptions (perfect mixing vs. partial mixing) in disordered media, as well as the predictive capacity of network modeling as a whole for ordered media are conducted. A mortar domain decomposition framework is additionally developed, under which efficient and accurate simulations on even larger and highly heterogeneous pore-scale domains are feasible. The mortar methods are verified and parallel scalability is demonstrated. It is shown that they can be used as “hybrid” methods for coupling localized pore-scale inclusions to a surrounding continuum (when insufficient scale separation exists). The framework further permits multi-model simulations within the same computational domain. An application of the methods studying “emergent” behavior during calcite precipitation in the context of geologic CO₂ sequestration is provided.Petroleum and Geosystems Engineerin

The ATLAS Level-1 Calorimeter Trigger

The ATLAS Level-1 Calorimeter Trigger uses reduced-granularity information from all the ATLAS calorimeters to search for high transverse-energy electrons, photons, tau leptons and jets, as well as high missing and total transverse energy. The calorimeter trigger electronics has a fixed latency of about 1 microsecond, using programmable custom-built digital electronics. This paper describes the Calorimeter Trigger hardware, as installed in the ATLAS electronics cavern

Optoelectronic devices and packaging for information photonics

This thesis studies optoelectronic devices and the integration of these components onto optoelectronic multi chip modules (OE-MCMs) using a combination of packaging techniques. For this project, (1×12) array photodetectors were developed using PIN diodes with a GaAs/AlGaAs strained layer structure. The devices had a pitch of 250μm, operated at a wavelength of 850nm. Optical characterisation experiments of two types of detector arrays (shoe and ring) were successfully performed. Overall, the shoe devices achieved more consistent results in comparison with ring diodes, i.e. lower dark current and series resistance values. A decision was made to choose the shoe design for implementation into the high speed systems demonstrator. The (1x12) VCSEL array devices were the optical sources used in my research. This was an identical array at 250μm pitch configuration used in order to match the photodetector array. These devices had a wavelength of 850nm. Optoelectronic testing of the VCSEL was successfully conducted, which provided good beam profile analysis and I-V-P measurements of the VCSEL array. This was then implemented into a simple demonstrator system, where eye diagrams examined the systems performance and characteristics of the full system and showed positive results. An explanation was given of the following optoelectronic bonding techniques: Wire bonding and flip chip bonding with its associated technologies, i.e. Solder, gold stud bump and ACF. Also, technologies, such as ultrasonic flip chip bonding and gold micro-post technology were looked into and discussed. Experimental work implementing these methods on packaging the optoelectronic devices was successfully conducted and described in detail. Packaging of the optoelectronic devices onto the OEMCM was successfully performed. Electrical tests were successfully carried out on the flip chip bonded VCSEL and Photodetector arrays. These results verified that the devices attached on the MCM achieved good electrical performance and reliable bonding. Finally, preliminary testing was conducted on the fully assembled OE-MCMs. The aim was to initially power up the mixed signal chip (VCSEL driver), and then observe the VCSEL output

Autonomous mobile materials handling platform architecture for mass customisation.

Thesis (M.Sc.Eng.)-University of KwaZulu-Natal, Durban, 2008.In order to facilitate the materials handling requirements of production structures configured for Mass Customisation Manufacturing, the design of requisite materials handling and routing systems must encompass new conceptual properties. Materials handling and routing systems with the capacity to support higher-level management systems would allow for mediated task allocation and structured vertical integration of these systems into existing manufacturing execution and management systems. Thus, a global objective in designing a materials handling and routing system, for such production configurations. is to provide a flexible system mechanism with minimal policy on system usage. With the recent developments in mobile robot technologies, due to various advancements in embedded system, computational, and communication infrastructures, mobile robot platforms can be developed that are robust and reliable, with operating structures incorporating bounded autonomy. With the addition of materials handling hardware, autonomous agent architectures, structured communication protocols and robotic software systems, these mobile robot platforms can provide viable solution mechanisms in realising real-time flexible materials handling in production environments facilitating Mass Customisation Manufacturing. This dissertation covers the research and development of a materials handling and routing system implementation architecture, for production environments facilitating Mass Customisation Manufacturing. The materials handling and routing task environment in such production structures is characterised in order to provide a well defined problem space for research purposes. A physical instance of a functional subset of the architecture is constructed consisting of a semi-autonomous mobile robot platform equipped with the infrastructure for materials handling and routing task execution. The architecture orientates the mobile robot platform in such a way as to present a collection of functional units, integrated and configured for a range of applications, and prevents viewpoints in the sense of monolithic mobile robots less susceptible to reconfiguration and stochastic utilisation

A complete design path for the layout of flexible macros

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An accurate analysis for guaranteed performance of multiprocessor streaming applications

Already for more than a decade, consumer electronic devices have been available for entertainment, educational, or telecommunication tasks based on multimedia streaming applications, i.e., applications that process streams of audio and video samples in digital form. Multimedia capabilities are expected to become more and more commonplace in portable devices. This leads to challenges with respect to cost efficiency and quality. This thesis contributes models and analysis techniques for improving the cost efficiency, and therefore also the quality, of multimedia devices. Portable consumer electronic devices should feature flexible functionality on the one hand and low power consumption on the other hand. Those two requirements are conflicting. Therefore, we focus on a class of hardware that represents a good trade-off between those two requirements, namely on domain-specific multiprocessor systems-on-chip (MP-SoC). Our research work contributes to dynamic (i.e., run-time) optimization of MP-SoC system metrics. The central question in this area is how to ensure that real-time constraints are satisfied and the metric of interest such as perceived multimedia quality or power consumption is optimized. In these cases, we speak of quality-of-service (QoS) and power management, respectively. In this thesis, we pursue real-time constraint satisfaction that is guaranteed by the system by construction and proven mainly based on analytical reasoning. That approach is often taken in real-time systems to ensure reliable performance. Therefore the performance analysis has to be conservative, i.e. it has to use pessimistic assumptions on the unknown conditions that can negatively influence the system performance. We adopt this hypothesis as the foundation of this work. Therefore, the subject of this thesis is the analysis of guaranteed performance for multimedia applications running on multiprocessors. It is very important to note that our conservative approach is essentially different from considering only the worst-case state of the system. Unlike the worst-case approach, our approach is dynamic, i.e. it makes use of run-time characteristics of the input data and the environment of the application. The main purpose of our performance analysis method is to guide the run-time optimization. Typically, a resource or quality manager predicts the execution time, i.e., the time it takes the system to process a certain number of input data samples. When the execution times get smaller, due to dependency of the execution time on the input data, the manager can switch the control parameter for the metric of interest such that the metric improves but the system gets slower. For power optimization, that means switching to a low-power mode. If execution times grow, the manager can set parameters so that the system gets faster. For QoS management, for example, the application can be switched to a different quality mode with some degradation in perceived quality. The real-time constraints are then never violated and the metrics of interest are kept as good as possible. Unfortunately, maintaining system metrics such as power and quality at the optimal level contradicts with our main requirement, i.e., providing performance guarantees, because for this one has to give up some quality or power consumption. Therefore, the performance analysis approach developed in this thesis is not only conservative, but also accurate, so that the optimization of the metric of interest does not suffer too much from conservativity. This is not trivial to realize when two factors are combined: parallel execution on multiple processors and dynamic variation of the data-dependent execution delays. We achieve the goal of conservative and accurate performance estimation for an important class of multiprocessor platforms and multimedia applications. Our performance analysis technique is realizable in practice in QoS or power management setups. We consider a generic MP-SoC platform that runs a dynamic set of applications, each application possibly using multiple processors. We assume that the applications are independent, although it is possible to relax this requirement in the future. To support real-time constraints, we require that the platform can provide guaranteed computation, communication and memory budgets for applications. Following important trends in system-on-chip communication, we support both global buses and networks-on-chip. We represent every application as a homogeneous synchronous dataflow (HSDF) graph, where the application tasks are modeled as graph nodes, called actors. We allow dynamic datadependent actor execution delays, which makes HSDF graphs very useful to express modern streaming applications. Our reason to consider HSDF graphs is that they provide a good basic foundation for analytical performance estimation. In this setup, this thesis provides three major contributions: 1. Given an application mapped to an MP-SoC platform, given the performance guarantees for the individual computation units (the processors) and the communication unit (the network-on-chip), and given constant actor execution delays, we derive the throughput and the execution time of the system as a whole. 2. Given a mapped application and platform performance guarantees as in the previous item, we extend our approach for constant actor execution delays to dynamic datadependent actor delays. 3. We propose a global implementation trajectory that starts from the application specification and goes through design-time and run-time phases. It uses an extension of the HSDF model of computation to reflect the design decisions made along the trajectory. We present our model and trajectory not only to put the first two contributions into the right context, but also to present our vision on different parts of the trajectory, to make a complete and consistent story. Our first contribution uses the idea of so-called IPC (inter-processor communication) graphs known from the literature, whereby a single model of computation (i.e., HSDF graphs) are used to model not only the computation units, but also the communication unit (the global bus or the network-on-chip) and the FIFO (first-in-first-out) buffers that form a ‘glue’ between the computation and communication units. We were the first to propose HSDF graph structures for modeling bounded FIFO buffers and guaranteed throughput network connections for the network-on-chip communication in MP-SoCs. As a result, our HSDF models enable the formalization of the on-chip FIFO buffer capacity minimization problem under a throughput constraint as a graph-theoretic problem. Using HSDF graphs to formalize that problem helps to find the performance bottlenecks in a given solution to this problem and to improve this solution. To demonstrate this, we use the JPEG decoder application case study. Also, we show that, assuming constant – worst-case for the given JPEG image – actor delays, we can predict execution times of JPEG decoding on two processors with an accuracy of 21%. Our second contribution is based on an extension of the scenario approach. This approach is based on the observation that the dynamic behavior of an application is typically composed of a limited number of sub-behaviors, i.e., scenarios, that have similar resource requirements, i.e., similar actor execution delays in the context of this thesis. The previous work on scenarios treats only single-processor applications or multiprocessor applications that do not exploit all the flexibility of the HSDF model of computation. We develop new scenario-based techniques in the context of HSDF graphs, to derive the timing overlap between different scenarios, which is very important to achieve good accuracy for general HSDF graphs executing on multiprocessors. We exploit this idea in an application case study – the MPEG-4 arbitrarily-shaped video decoder, and demonstrate execution time prediction with an average accuracy of 11%. To the best of our knowledge, for the given setup, no other existing performance technique can provide a comparable accuracy and at the same time performance guarantees

Robust and stochastic approaches to network capacity design under demand uncertainty

This thesis considers the network capacity design problem with demand uncertainty using the stochastic, robust and distributionally robust stochastic optimization approaches (DRSO). Network modeling in itself has found wide areas of application in most fields of human endeavor. The network would normally consist of source (origin) and sink (destination) nodes connected by arcs that allow for flows of an entity from the origin to the destination nodes. In this thesis, a special type of the minimum cost flow problem is addressed, the multi-commodity network flow problem. Commodities are the flow types that are transported on a shared network. Offered demands are, for the most part, unknown or uncertain, hence a model that immune against this uncertainty becomes the focus as well as the practicability of such models in the industry. This problem falls under the two-stage optimization framework where a decision is delayed in time to adjust for the first decision earlier made. The first stage decision is called the "here and now", while the second stage traffic re-adjustment is the "wait and see" decision. In the literature, the decision-maker is often believed to know the shape of the uncertainty, hence we address this by considering a data-driven uncertainty set. The research also addressed the non-linearity of cost function despite the abundance of literature assuming linearity and models proposed for this. This thesis consist of four main chapters excluding the "Introduction" chapter and the "Approaches to Optimization under Uncertainty" chapter where the methodologies are reviewed. The first of these four, Chapter 3, proposes the two models for the Robust Network Capacity Expansion Problem (RNCEP) with cost non-linearity. These two are the RNCEP with fixed-charge cost and RNCEP with piecewise-linear cost. The next chapter, Chapter 4, compares the RNCEP models under two types of uncertainties in order to address the issue of usefulness in a real world setting. The resulting two robust models are also comapared with the stochastic optimization model with distribution mean. Chapter 5 re-examines the earlier problem using machine learning approaches to generate the two uncertainty sets while the last of these chapters, Chapter 6, investigates DRSO model to network capacity planning and proposes an efficient solution technique