17,554 research outputs found
On the Verification of a WiMax Design Using Symbolic Simulation
In top-down multi-level design methodologies, design descriptions at higher
levels of abstraction are incrementally refined to the final realizations.
Simulation based techniques have traditionally been used to verify that such
model refinements do not change the design functionality. Unfortunately, with
computer simulations it is not possible to completely check that a design
transformation is correct in a reasonable amount of time, as the number of test
patterns required to do so increase exponentially with the number of system
state variables. In this paper, we propose a methodology for the verification
of conformance of models generated at higher levels of abstraction in the
design process to the design specifications. We model the system behavior using
sequence of recurrence equations. We then use symbolic simulation together with
equivalence checking and property checking techniques for design verification.
Using our proposed method, we have verified the equivalence of three WiMax
system models at different levels of design abstraction, and the correctness of
various system properties on those models. Our symbolic modeling and
verification experiments show that the proposed verification methodology
provides performance advantage over its numerical counterpart.Comment: In Proceedings SCSS 2012, arXiv:1307.802
A generic debug interface for IP-integrated assertions
Der Entwurf von Hardware/Software Systemen ist auf eine solide
Verifikationsmethodik angewiesen, die den ganzen Design Flow durchzieht.
Viele Konzepte haben eine Erhöhung des Abstraktionsniveaus bei der
Entwurfseingabe gemeinsam, wobei der modell-basierte Hardware-Entwurf einen
vielversprechenden und sich verbreitenenden Ansatz darstellt. Assertion
basierte Verifikation ermöglicht dem Entwickler die Spezifikation von
Eigenschaften des Entwurfes und die Aufdeckung von Fällen, in denen diese
verletzt werden. Während Assertions in Entwurfs- und Simulationsstadien
weit verbreitet sind, ist der Ansatz, diese mit auf dem integrierten
Schaltkreis (IC) zu fertigen, neuartig. In dieser Diplomarbeit soll ein von
Infineon Technologies entwickeltes, auf UML basierendes Datenmodell,
welches zur Erfassung von Entwurfsspezifikation und zur automatischen
Code-Generierung genutzt wird dahingehend erweitert werden, die
Beschreibung für im IC integrierte Assertions zu ermöglichen. Für diese
Zwecke wird ein abstraktes Datenmodell beschrieben werden. Das Assertion
Interface soll die spezifikationsgetreue Modellintegration gewährleisten,
sowie IC interne Assertionresultate dem umgebenen System über das Interface
zugänglich machen und damit zum Debugging während der Laufzeit ermöglichen.
Ferner werden die Codegenerierungs Templates erläutert und
einBeispielsystem eingeführt, um die beschriebenden Konzepte zu validieren.Nowadays electronic systems design requires fast time to market and solid verification throughout the entire design flow. Many concepts have been researched to raise the level of abstraction during the design entry phase, whereas model-based design is the most promising one. Assertion-based verification enables the developer to specify properties of the design and to get report if these are violated. Assertions are common during development and simulation of electronic products but often are not included in the final silicon. In this thesis an UML-based model defined at Infineon Technologies for capturing design specification information and to generate code automatically using templates, will be extended to allow the description of an abstract debuggable assertion interface for silicon assertions. With help of the assertion interface it shall be possible to verify the correct module integration and to monitor IP-internal assertion checker results. Besides, the code-generation templates for the assertion interface model will be described. To demonstrate the usability of the developed concepts an example system will be introduced to validate the approach.Ilmenau, Techn. Univ., Diplomarbeit, 200
From FPGA to ASIC: A RISC-V processor experience
This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC
High-level modelling languages
This paper gives an introduction to the latest developments in modern electronic design methodology. It will give a brief history of the evolution of design software in an attempt to explain the seemingly haphazard development up to the present-day situation
Formal Verification of Probabilistic SystemC Models with Statistical Model Checking
Transaction-level modeling with SystemC has been very successful in
describing the behavior of embedded systems by providing high-level executable
models, in which many of them have inherent probabilistic behaviors, e.g.,
random data and unreliable components. It thus is crucial to have both
quantitative and qualitative analysis of the probabilities of system
properties. Such analysis can be conducted by constructing a formal model of
the system under verification and using Probabilistic Model Checking (PMC).
However, this method is infeasible for large systems, due to the state space
explosion. In this article, we demonstrate the successful use of Statistical
Model Checking (SMC) to carry out such analysis directly from large SystemC
models and allow designers to express a wide range of useful properties. The
first contribution of this work is a framework to verify properties expressed
in Bounded Linear Temporal Logic (BLTL) for SystemC models with both timed and
probabilistic characteristics. Second, the framework allows users to expose a
rich set of user-code primitives as atomic propositions in BLTL. Moreover,
users can define their own fine-grained time resolution rather than the
boundary of clock cycles in the SystemC simulation. The third contribution is
an implementation of a statistical model checker. It contains an automatic
monitor generation for producing execution traces of the
model-under-verification (MUV), the mechanism for automatically instrumenting
the MUV, and the interaction with statistical model checking algorithms.Comment: Journal of Software: Evolution and Process. Wiley, 2017. arXiv admin
note: substantial text overlap with arXiv:1507.0818
A multi-paradigm language for reactive synthesis
This paper proposes a language for describing reactive synthesis problems
that integrates imperative and declarative elements. The semantics is defined
in terms of two-player turn-based infinite games with full information.
Currently, synthesis tools accept linear temporal logic (LTL) as input, but
this description is less structured and does not facilitate the expression of
sequential constraints. This motivates the use of a structured programming
language to specify synthesis problems. Transition systems and guarded commands
serve as imperative constructs, expressed in a syntax based on that of the
modeling language Promela. The syntax allows defining which player controls
data and control flow, and separating a program into assumptions and
guarantees. These notions are necessary for input to game solvers. The
integration of imperative and declarative paradigms allows using the paradigm
that is most appropriate for expressing each requirement. The declarative part
is expressed in the LTL fragment of generalized reactivity(1), which admits
efficient synthesis algorithms, extended with past LTL. The implementation
translates Promela to input for the Slugs synthesizer and is written in Python.
The AMBA AHB bus case study is revisited and synthesized efficiently,
identifying the need to reorder binary decision diagrams during strategy
construction, in order to prevent the exponential blowup observed in previous
work.Comment: In Proceedings SYNT 2015, arXiv:1602.0078
From Monologue to Dialogue: Natural Language Generation in OVIS
This paper describes how a language generation system that was originally designed for monologue generation, has been adapted for use in the OVIS spoken dialogue system. To meet the requirement that in a dialogue, the system's utterances should make up a single, coherent dialogue turn, several modifications had to be made to the system. The paper also discusses the influence of dialogue context on information status, and its consequences for the generation of referring expressions and accentuation
Verification of the FtCayuga fault-tolerant microprocessor system. Volume 1: A case study in theorem prover-based verification
The design and formal verification of a hardware system for a task that is an important component of a fault tolerant computer architecture for flight control systems is presented. The hardware system implements an algorithm for obtaining interactive consistancy (byzantine agreement) among four microprocessors as a special instruction on the processors. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, provided certain preconditions hold. An assumption is made that the processors execute synchronously. For verification, the authors used a computer aided design hardware design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover
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