An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing

This brief presents an ultra-low power low-dropout (LDO) regulator with an experimental total quiescent current consumption of only 3.08 nA. The circuit is designed to operate with a load current in the range 0 - 11 mA. A novel adaptive biasing scheme based on a super source follower (SSF) structure is proposed, which measures the absolute voltage difference between the two inputs of the LDO’s error amplifier and modifies the biasing current accordingly. Thus, the transient response of the regulator is improved by counteracting the effect of using such a low bias current. The proposed LDO has been fabricated in a standard CMOS 180 nm process and the experimental characterization showed an outstanding performance in terms of maximum load current over quiescent current consumption ratio.S

A Fast Transient Response and High PSR Low Drop-Out Voltage Regulator

In this paper, a low drop-out (LDO) linear regulator with high power supply rejection ratio(PSR) and fast transient response is proposed for various applications. To achieve fast transient response, this work employs variable bias and transient-boost capacitance. The variable bias structure enhance the slew rate and PSR of LDO. The transient-boost capacitance (TBC) is set in a proper location, using its voltage characteristic to enhance transient response without consuming quiescent current, and it also improves circuit's stability. This circuit is designed based on TSMC 65nm CMOS Technology and verified by Cadence simulation environment. According to the simulation results, the LDO achieves a PSR of 68.3dB and 51.4dB at 10kHz and 1MHz. Undershoot and overshoot of Vout are 190mV and 143mV under a varying load current from 20mA to 80mA with edge time of 1ns

0.6-V-VIN 7.0-nA-IQ 0.75-mA-IL CMOS Capacitor-Less LDO for Low-Voltage Micro-Energy-Harvested Supplies

A capacitor-less (CL) low-dropout (LDO) regulator suitable to be incorporated in an on-chip system with low-voltage micro-energy-harvested supply, is proposed in this contribution. The differential input stage of the error amplifier includes bulk-driven MOS transistors, thus providing the LDO with an output voltage range that extends from the negative rail up to a level very close to the input voltage without the need of using a resistive feedback network. The circuit parameters relying on the feedback factor, , are maximized thanks to the use of a unitary value for this parameter. The CL-LDO has been designed and fabricated in standard 180-nm CMOS technology and optimized to operate with an input voltage equal to 0.6 V and a reference level of 0.5 V. The experimental characterization of the fabricated prototypes shows that, under these operating conditions, the LDO is able to deliver a load current above 0.75 mA with a total quiescent current of only 7.0 nA. Furthermore, the proposed voltage regulator is able to operate from input voltages as low as 0.4 V, delivering in this case a maximum load current of 30 μA.RTI2018- 095994-B-I00 ED431G-2019/04 GRC2021/48 IB18079S

Design of low-dropout regulator for ultra low power on-chip applications

Low Drop Out (LDO) voltage regulators are commonly used to supply low-voltage digital circuits such as microprocessor cores. These digital circuits normally are continuously changing from one mode of operation to another. Therefore, the load demand can change rapidly resulting in large voltage transients at the output of the regulator which can adversely affect the digital circuitry. In this Master's Thesis, design topologies and challenges of very low-power fully integrated On-Chip Low-Dropout (LDO) regulators have been analyzed. Instead of conventional LDO which makes use of a large external capacitor to have better dynamic response and stability, a CapacitorLess LDO (CL-LDO) is chosen on considerations of smaller area. The most challenging part of designing this kind of regulator is achieving high current efficiency by reducing the quiescent current while ensuring good stability response as well as good regulation performance. Thus, different circuit techniques must be carefully added in order to balance the lack of the large external capacitor having the minimum impact on system efficiency. This work focuses on designing a fully integrated low-dropout regulator with good dynamic performance, high regulation performance and ultra-low power consumption. The stability is achieved by the use of two pole-splitting techniques, namely Cascode and Nested-Miller compensation. The good dynamic response with low quiescent current are achieved by the use of an adaptive biasing circuit, a gm-boost circuit and adaptive power transistor architecture

CMOS Design of Reconfigurable SoC Systems for Impedance Sensor Devices

La rápida evolución en el campo de los sensores inteligentes, junto con los avances en las tecnologías de la computación y la comunicación, está revolucionando la forma en que recopilamos y analizamos datos del mundo físico para tomar decisiones, facilitando nuevas soluciones que desempeñan tareas que antes eran inconcebibles de lograr.La inclusión en un mismo dado de silicio de todos los elementos necesarios para un proceso de monitorización y actuación ha sido posible gracias a los avances en micro (y nano) electrónica. Al mismo tiempo, la evolución de las tecnologías de procesamiento y micromecanizado de superficies de silicio y otros materiales complementarios ha dado lugar al desarrollo de sensores integrados compatibles con CMOS, lo que permite la implementación de matrices de sensores de alta densidad. Así, la combinación de un sistema de adquisición basado en sensores on-Chip, junto con un microprocesador como núcleo digital donde se puede ejecutar la digitalización de señales, el procesamiento y la comunicación de datos proporciona características adicionales como reducción del coste, compacidad, portabilidad, alimentación por batería, facilidad de uso e intercambio inteligente de datos, aumentando su potencial número de aplicaciones.Esta tesis pretende profundizar en el diseño de un sistema portátil de medición de espectroscopía de impedancia de baja potencia operado por batería, basado en tecnologías microelectrónicas CMOS, que pueda integrarse con el sensor, proporcionando una implementación paralelizable sin incrementar significativamente el tamaño o el consumo, pero manteniendo las principales características de fiabilidad y sensibilidad de un instrumento de laboratorio. Esto requiere el diseño tanto de la etapa de gestión de la energía como de las diferentes celdas que conforman la interfaz, que habrán de satisfacer los requisitos de un alto rendimiento a la par que las exigentes restricciones de tamaño mínimo y bajo consumo requeridas en la monitorización portátil, características que son aún más críticas al considerar la tendencia actual hacia matrices de sensores.A nivel de celdas, se proponen diferentes circuitos en un proceso CMOS de 180 nm: un regulador de baja caída de voltaje como unidad de gestión de energía, que proporciona una alimentación de 1.8 V estable, de bajo ruido, precisa e independiente de la carga para todo el sistema; amplificadores de instrumentación con una aproximación completamente diferencial, que incluyen una etapa de entrada de voltaje/corriente configurable, ganancia programable y ancho de banda ajustable, tanto en la frecuencia de corte baja como alta; un multiplicador para conformar la demodulación dual, que está embebido en el amplificador para optimizar consumo y área; y filtros pasa baja totalmente integrados, que actúan como extractores de magnitud de DC, con frecuencias de corte ajustables desde sub-Hz hasta cientos de Hz.<br /

Design of a 20 mA Capless LDO for IoT systems

In recent years, there has been a breakthrough in integrated circuit technology, which has enabled the full integration of systems on a single chip and the development of increas ingly compact and low-power devices, such as IoT devices and smart devices. Usually, these devices come equipped with sensors and transceivers that make the interaction between the analog world and the digital world. In some of these devices Delta-Sigma modeling ( ∆Σ) is used to make the conversion from analogue to digital (ADC). In addition, the linear voltage regulator Low Dropout (LDO) is commonly used as the reference voltage buffer for the ADC ∆Σ. Since it is intended to do full system integra tion on a chip it is necessary to perform LDO integration. However, the LDO usually requires an external capacitor on the order of micro Farads to ensure stability, which makes integration of this circuit impossible. Currently, there are studies of LDO that do not need an external capacitor to be integrated into a chip. Among the proposals analyzed, it was found that some LDO are designed to have fast transient response and others, high PSRR. However, designing an LDO with these characteristics comes with new challenges such as ensuring stability, preventing PSRR degradation, and ensuring the speed of the transient response without causing an increase in the power consumed by the LDO. Traditionally, between the LDO and the ADC there is a switch switching very quickly, knowing the switching interval of the switch. Thus, in the present study a new architec ture is presented, based on the traditional LDO, but with a Miller compensation circuit that adapts to the load current. This compensation circuit allows to guarantee the sta bility and transient response of the circuit in each state of the current in the load. The developed LDO can achieve a gain of 77.3 dB, the PSRR at frequency of 1 kHz is 78.72 dB, when the IL = 20 .T hecurrentconsumedbytheLDOis IQ = 49.69 microA and when the switch between the LDO and the ADC is turned on, the IL transitions from 0 Ato20 milliA and takes 77.71 nanos until it stabilizes and provides a stable voltage to the ADC.Nos últimos anos, tem se verificado um avanço na tecnologia dos circuitos integrados, que tem permitido fazer a integração total de sistemas num único chip e o desenvolvimento de dispositivos cada vez mais compactos e de baixa potência, como os dispositivos IoT e smart devices. Normalmente estes dispositivos vêm equipados com sensores e transcetores que fazem a interação entre o mundo analógico e mundo digital. Em alguns destes dispositivos é utilizada a modelação Delta-Sigma ( ∆Σ) para fazer a conversão do analógico para o digital (ADC). Para além disso, é comummente usado o regulador de tensão linear Low Dropout (LDO) como buffer de tensão de referência para o ADC ∆Σ. Como se pretende fazer a integração total do sistema num chip é necessário realizar a integração do LDO. Contudo, o LDO normalmente necessita de um condensador externo na ordem dos micro Farads para assegurar a estabilidade, o que impossibilita a integração deste circuito. Atualmente, existem estudos de LDO que não precisa de ter um condensador externo para se realizar a integração deste, num chip. Entre as propostas analisadas verificou-se que alguns LDO são desenvolvidos por forma a ter rápida resposta transitória e outros, elevado PSRR. Contudo, projetar um LDO com essas características vem com novos desafios como assegurar a estabilidade, prevenir a degradação do PSRR, e garantir a velocidade da resposta transitória sem causar o aumento da potência consumida pelo LDO. Tradicionalmente, entre o LDO e o ADC há um interruptor a comutar muito rapidamente, conhecendo-se o intervalo de comutação do interruptor. Desta forma, no presente estudo é apresentada uma nova arquitetura, baseada no LDO tradicional, mas com um circuito de compensação de Miller que se adapta à corrente da carga. Este circuito de compensação permite garantir a estabilidade e a resposta transitória do circuito em cada estado da corrente na carga. O LDO desenvolvido consegue atingir um ganho de 77,3 dB, o PSRR a frequência de 1 kHz é 78,72 dB, quando o IL = 20 mA. A corrente consumida pelo LDO é IQ = 49,69 µA e quando o interruptor entre o LDO e o ADC é ligado, o IL transita de 0A para 20 mA e demora 77,71 ns até estabilizar e fornecer uma tensão estável ao ADC

A high-speed low-dropout voltage regulator using a compact output driver

Orientadores: Elnatan Chagas Ferreira, Sandro Augusto Pavlik HaddadTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: Ao longo dos anos, microcontroladores tornaram-se mais rápidos e mais poderosos em sua capacidade de processamento graças à evolução dos processos de fabricação. Os novos processos CMOS de menores geometrias exigem tolerâncias menores quanto à tensão de ali-mentação. A lógica digital nesses dispositivos exige que o regulador interno forneça uma ten-são de alimentação estável e precisa, muitas vezes sem o auxílio de um capacitor externo de desacoplamento, o que torna o projeto do regulador uma tarefa árdua devido à natureza da carga digital. São milhões de portas lógicas comutando simultaneamente que ocasionam picos de corrente que podem atingir dezenas de vezes o valor médio do consumo de corrente. Como resultado, o regulador interno deve ser projetado para atender a esse perfil de carga, especial-mente durante as transições de modos de operação. Em outras palavras, quando o microcon-trolador sai de um modo de ultrabaixo consumo (de poucos microampères) para outro modo de operação de alto consumo de potência (dezenas ou centenas de miliampères) e vice-versa. Esse trabalho apresenta a implementação de um regulador LDO (low dropout) utilizan-do um dispositivo de saída NMOS que não sofre de problemas de estabilidade em altas fre-quências. A nova topologia alcança redução de área de silício significativa no estágio de saída e resposta transitória muito rápida para transições agressivas de carga, sem a necessidade de capacitor externo. Um protótipo do circuito proposto foi implementado em tecnologia CMOS split gate TFS (Thin Film Storage) de 90 nm. O silício foi encapsulado em QFP64 e avaliado em labora-tório nas dependências da NXP Semiconductors Brasil. Outra versão do circuito, em processo CMOS 55 nm, já está em produção, foi caracterizado e qualificado em ambiente automotivo. As medidas em laboratório demonstraram que o novo circuito responde extremamente rápido aos transientes de carga na versão fabricada em tecnologia CMOS 90 nm. Isso o torna apropri-ado para aplicações em microcontroladores (cargas predominantemente digitais). Na versão fabricada em 55 nm, mais de uma centena de peças foram medidas em pro-cesso (split lots) e temperatura e serviram para demonstrar que o circuito pode ser projetado também para aplicações focando baixo consumo energiaAbstract: Modern power management System-on-a-Chip (SoC) design demands for fully integrat-ed solutions in order to decrease certain costly features such as the total chip area and the power consumption while maintaining or increasing the regulator response during aggressive load variations. Low-Dropout (LDO) voltage regulators, as power management devices, must comply with these recent technological and industrial trends. On-chip embedded LDO voltage regulators have to deliver stable and accurate local supply voltages to digital circuits that draw large and fast slew-rate current peaks, characteris-tics that are difficult to implement when off-chip inductors and capacitors are not used. The structure and frequency compensation scheme of classical LDO regulators, especially with low-voltage designs, present a trade-off between stability and transient response of the LDO regulator. To improve load regulation under large and fast load variations in linear regulators, it is necessary to employ large area output drivers. Thus, besides stability issues, another diffi-culty in designing LDOs is to create a compact driver with good load regulation and a fast transient response under large load variations. This manuscript presents a novel topology of a capacitor-free CMOS LDO regulator utilizing a compact NMOS output driver. The new output driver cell achieves low voltage ripple and very fast transient response under large load steps with a small silicone area. The circuit has been implemented in a 90 nm CMOS process technology. Silicon results demonstrated a transient loop response faster than 30 ns to a load variation of four orders of magnitude. Another version of the circuit has been implemented in a 55 nm CMOS technology. Alt-hough primarily targeted to attain low power requirements, this version has been qualified to meet industry standard automotive specifications and is currently in production as part of the Power Management Controller (PMC) block integrated within a family of MCUs used in au-tomotive and industrial powertrainDoutoradoEletrônica, Microeletrônica e OptoeletrônicaDoutor em Engenharia Elétric

Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications

Software-defined radio receivers (SDRs) have become popular to accommodate multi-standard wireless services using a single chip-set solution in mobile telecommunication systems. In SDRs, the signal is down-converted to an intermediate frequency and then digitalized. This approach relaxes the specifications for most of the analog front-end building blocks by performing most of the signal processing in the digital domain. However, since the analog-to-digital converter (ADC) is located as close as possible to the antenna in SDR architectures, the ADC specification requirements are very stringent because a large amount of interference signals are present at the ADC input due to the removal of filtering blocks, which particularly affects the dynamic range (DR) specification. Sigma-delta (ΣΔ) ADCs have several benefits such as low implementation cost, especially when the architecture contains mostly digital circuits. Furthermore, continuous-time (CT) ΣΔ ADCs allow elimination of the anti‐aliasing filter because input signals are sampled after the integrator. The bandwidth requirements for the amplifiers in CT ΣΔ ADCs can be relaxed due to the continuous operation without stringing settling time requirements. Therefore, they are suitable for high‐speed and low‐power applications. In addition, CT ΣΔ ADCs achieve high resolution due to the ΣΔ modulator’s noise shaping property. However, the in-band quantization noise is shaped by the analog loop filter and the distortions of the analog loop filter directly affect the system output. Hence, highly linear low-noise loop filters are required for high-performance ΣΔ modulators. The first task in this research focused on using CMOS 90 nm technology to design and fabricate a 5^(TH)–order active-RC loop filter with a cutoff frequency of 20 MHz for a low pass (LP) CT ΣΔ modulator. The active-RC topology was selected because of the high DR requirement in SDR applications. The amplifiers in the first stage of the loop filter were implemented with linearization techniques employing anti-parallel cancellation and source degeneration in the second stage of the amplifiers. These techniques improve the third-order intermodulation (IM3) by approximately 10 dB; while noise, area, and power consumption do not increase by more than 10%. Second, a current-mode adder-flash ADC was also fabricated as part of a LP CT ΣΔ modulator. The new current-mode operation developed through this research makes possible a 53% power reduction. The new technology also lessens existing problems associated with voltage-mode flash ADCs, which are mainly related to voltage headroom restrictions, speed of operation, offsets, and power efficiency of the latches. The core of the current-mode adder-flash ADC was fabricated in CMOS 90 nm technology with 1.2 V supply; it dissipates 3.34 mW while operating at 1.48 GHz and consumes a die area of 0.0276 mm^(2). System-on chip (SoC) solutions are becoming more popular in mobile telecommunication systems to improve the portability and competitiveness of products. Since the analog/RF and digital blocks often share the same external power supply in SoC solutions, the on-chip generation of clean power supplies is necessary to avoid system performance degradation due to supply noises. Finally, the critical design issues for external capacitor-less low drop-out (LDO) regulators for SoC applications are addressed in this dissertation, especially the challenges related to power supply rejection at high frequencies as well as loop stability and transient response. The paths of the power supply noise to the LDO output were analyzed, and a power supply noise cancellation circuit was developed. The power supply rejection (PSR) performance was improved by using a replica circuit that tracks the main supply noise under process-voltage-temperature variations and all operating conditions. Fabricated in a 0.18 μm CMOS technology with 1.8 V supply, the entire proposed LDO consumes 55 μA of quiescent current while in standby operation, and it has a drop-out voltage of 200 mV when providing 50 mA to the load. Its active core chip area is 0.14 mm2. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respectively