9,805 research outputs found

    Demodulation Type Single-Phase PLL with DC Offset Rejection

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    Exploitation of Digital Filters to Advance the Single-Phase T/4 Delay PLL System

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    With the development of digital signal processing technologies, control and monitoring of power electronics conversion systems have been evolving to become fully digital. As the basic element in the design and analysis phases of digital controllers or filters, a number of unit delays (z-1) have been employed, e.g., in a cascaded structure. Practically, the number of unit delays is designed as an integer, which is related to the sampling frequency as well as the ac signal fundamental frequency (e.g., 50 Hz). More common, the sampling frequency is fixed during operation for simplicity and design. Hence, any disturbance in the ac signal will violate this design rule and it can become a major challenge for digital controllers. To deal with the above issue, this paper first exploits a virtual unit delay (zv-1) to emulate the variable sampling behavior in practical digital signal processors with a fixed sampling rate. This exploitation is demonstrated on a T/4 Delay Phase Locked Loop (PLL) system for a single-phase grid-connected inverter. The T/4 Delay PLL requires to cascade 50 unit delays when implemented (for a 50-Hz system with 10 kHz sampling frequency). Furthermore, digital frequency adaptive comb filters are adopted to enhance the performance of the T/4 Delay PLL when the grid suffers from harmonics. Experimental results have confirmed the effectiveness of the digital filters for advanced control systems

    Adaptive multibeam phased array design for a Spacelab experiment

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    The parametric tradeoff analyses and design for an Adaptive Multibeam Phased Array (AMPA) for a Spacelab experiment are described. This AMPA Experiment System was designed with particular emphasis to maximize channel capacity and minimize implementation and cost impacts for future austere maritime and aeronautical users, operating with a low gain hemispherical coverage antenna element, low effective radiated power, and low antenna gain-to-system noise temperature ratio

    DSN advanced receiver: Breadboard description and test results

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    A breadboard Advanced Receiver for use in the Deep Space Network was designed, built, and tested in the laboratory. Field testing was also performed during Voyager Uranus encounter at DSS-13. The development of the breadboard is intended to lead towards implementation of the new receiver throughout the network. The receiver is described on a functional level and then in terms of more specific hardware and software architecture. The results of performance tests in the laboratory and in the field are given. Finally, there is a discussion of suggested improvements for the next phase of development

    Comparative Performance Evaluation of Orthogonal-Signal-Generators-Based Single-Phase PLL Algorithms:A Survey

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    Performance Evaluation of Type-3 PLLs Under Wide Variation in Input Voltage and Frequency

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    Phase-coherent lightwave communications with frequency combs

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    Fiber-optical networks are a crucial telecommunication infrastructure in society. Wavelength division multiplexing allows for transmitting parallel data streams over the fiber bandwidth, and coherent detection enables the use of sophisticated modulation formats and electronic compensation of signal impairments. In the future, optical frequency combs may replace multiple lasers used for the different wavelength channels. We demonstrate two novel signal processing schemes that take advantage of the broadband phase coherence of optical frequency combs. This approach allows for a more efficient estimation and compensation of optical phase noise in coherent communication systems, which can significantly simplify the signal processing or increase the transmission performance. With further advances in space division multiplexing and chip-scale frequency comb sources, these findings pave the way for compact energy-efficient optical transceivers.Comment: 17 pages, 9 figure

    Robust PLL Synchronization Unit for Grid-Feeding Converters in Micro/Weak Grids

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    A grid-feeding voltage source converter (GFD-VSC) requires a phase-locked loop (PLL) synchronization unit to be connected to the grid. The PLL critically affects the dynamic performance and stability of the GFD-VSC. In particular, a PLL with in-loop filtering, for working under distorted/polluted conditions, possesses a narrow stability margin and deficient performance in weak grid connections and fault ride-through (FRT) transients, also poor performance in frequency estimation. To address these problems, for the first time, a robust PLL with several enhanced characteristics is proposed in this paper. The robust PLL with a dynamic state feedback controller is designed using an H∞ robust control. The feedback controller is designed to improve the dynamic stability/response of the PLL, exposed to control uncertainties and exogenous disturbances, weak-grid connection, FRT transients and to improve its performance in frequency estimation. Numerical simulations validate the effectiveness of the proposed PLL
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