OPTIMIZING LARGE COMBINATIONAL NETWORKS FOR K-LUT BASED FPGA MAPPING

Optimizing by partitioning is a central problem in VLSI design automation, addressing circuit’s manufacturability. Circuit partitioning has multiple applications in VLSI design. One of the most common is that of dividing combinational circuits (usually large ones) that will not fit on a single package among a number of packages. Partitioning is of practical importance for k-LUT based FPGA circuit implementation. In this work is presented multilevel a multi-resource partitioning algorithm for partitioning large combinational circuits in order to efficiently use existing and commercially available FPGAs packagestwo-way partitioning, multi-way partitioning, recursive partitioning, flat partitioning, critical path, cutting cones, bottom-up clusters, top-down min-cut

Reformulated acyclic partitioning for rail-rail containers transshipment

Many rail terminals have loading areas that are properly equipped to move containers between trains. With the growing throughput of these terminals all the trains involved in a sequence of such movements may not ¿t in the loading area simultaneously, and storage areas are needed to place containers waiting for their destination train, although this storage increases the cost of the transshipment. This increases the complexity of the planning decisions concerning these activities, since now trains need to be packed in groups that ¿t in the loading area, in such a way that the number of containers moved to the storage area is minimized. Additionally, each train is only allowed to enter the loading area once. Similarly to previous authors, we model this situation as an acyclic graph partitioning problem for which we present a new formulation, and several valid inequalities based on its theoretical properties. Our computational experiments show that the new formulation outperforms the previously existing ones, providing results that improve even on the best exact algorithm designed so far for this problem.Peer ReviewedPostprint (author's final draft

Delay driven multi-way circuit partitioning.

Wong Sze Hon.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.Includes bibliographical references (leaves 88-91).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Preliminaries --- p.1Chapter 1.2 --- Motivations --- p.1Chapter 1.3 --- Contributions --- p.3Chapter 1.4 --- Organization of the Thesis --- p.4Chapter 2 --- VLSI Physical Design Automation --- p.5Chapter 2.1 --- Preliminaries --- p.5Chapter 2.2 --- VLSI Design Cycle [1] --- p.6Chapter 2.2.1 --- System Specification --- p.6Chapter 2.2.2 --- Architectural Design --- p.6Chapter 2.2.3 --- Functional Design --- p.6Chapter 2.2.4 --- Logic Design --- p.8Chapter 2.2.5 --- Circuit Design --- p.8Chapter 2.2.6 --- Physical Design --- p.8Chapter 2.2.7 --- Fabrication --- p.8Chapter 2.2.8 --- Packaging and Testing --- p.9Chapter 2.3 --- Physical Design Cycle [1] --- p.9Chapter 2.3.1 --- Partitioning --- p.9Chapter 2.3.2 --- Floorplanning and Placement --- p.11Chapter 2.3.3 --- Routing --- p.11Chapter 2.3.4 --- Compaction --- p.12Chapter 2.3.5 --- Extraction and Verification --- p.12Chapter 2.4 --- Chapter Summary --- p.12Chapter 3 --- Recent Approaches on Circuit Partitioning --- p.14Chapter 3.1 --- Preliminaries --- p.14Chapter 3.2 --- Circuit Representation --- p.15Chapter 3.3 --- Delay Modelling --- p.16Chapter 3.4 --- Partitioning Objectives --- p.19Chapter 3.4.1 --- Interconnections between Partitions --- p.19Chapter 3.4.2 --- Delay Minimization --- p.19Chapter 3.4.3 --- Area and Number of Partitions --- p.20Chapter 3.5 --- Partitioning Algorithms --- p.20Chapter 3.5.1 --- Cut-size Driven Partitioning Algorithm --- p.21Chapter 3.5.2 --- Delay Driven Partitioning Algorithm --- p.32Chapter 3.5.3 --- Acyclic Circuit Partitioning Algorithm --- p.33Chapter 4 --- Clustering Based Acyclic Multi-way Partitioning --- p.38Chapter 4.1 --- Preliminaries --- p.38Chapter 4.2 --- Previous Works on Clustering Based Partitioning --- p.39Chapter 4.2.1 --- Multilevel Circuit Partitioning [2] --- p.40Chapter 4.2.2 --- Cluster-Oriented Iterative-Improvement Partitioner [3] --- p.42Chapter 4.2.3 --- Section Summary --- p.44Chapter 4.3 --- Problem Formulation --- p.45Chapter 4.4 --- Clustering Based Acyclic Multi-Way Partitioning --- p.46Chapter 4.5 --- Modified Fan-out Free Cone Decomposition --- p.47Chapter 4.6 --- Clustering Phase --- p.48Chapter 4.7 --- Partitioning Phase --- p.51Chapter 4.8 --- The Acyclic Constraint --- p.52Chapter 4.9 --- Experimental Results --- p.57Chapter 4.10 --- Chapter Summary --- p.58Chapter 5 --- Network Flow Based Multi-way Partitioning --- p.61Chapter 5.1 --- Preliminaries --- p.61Chapter 5.2 --- Notations and Definitions --- p.62Chapter 5.3 --- Net Modelling --- p.63Chapter 5.4 --- Previous Works on Network Flow Based Partitioning --- p.64Chapter 5.4.1 --- Network Flow Based Min-Cut Balanced Partitioning [4] --- p.65Chapter 5.4.2 --- Network Flow Based Circuit Partitioning for Time-multiplexed FPGAs [5] --- p.66Chapter 5.5 --- Proposed Net Modelling --- p.70Chapter 5.6 --- Partitioning Properties Based on the Proposed Net Modelling --- p.73Chapter 5.7 --- Partitioning Step --- p.75Chapter 5.8 --- Constrained FM Post Processing Step --- p.79Chapter 5.9 --- Experiment Results --- p.81Chapter 6 --- Conclusion --- p.86Bibliography --- p.8

Acyclic partitioning of large directed acyclic graphs

We investigate the problem of partitioning the vertices of a directed acyclic graph into a given number of parts. The objective function is to minimize the number or the total weight of the edges having end points in different parts, which is also known as edge cut. The standard load balancing constraint of having an equitable partition of the vertices among the parts should be met. Furthermore, the partition is required to be acyclic, i.e., the inter-part edges between the vertices from different parts should preserve an acyclic dependency structure among the parts. In this work, we adopt the multilevel approach with coarsening, initial partitioning, and refinement phases for acyclic partitioning of directed acyclic graphs. We focus on two-way partitioning (sometimes called bisection), as this scheme can be used in a recursive way for multi-way partitioning. To ensure the acyclicity of the partition at all times, we propose novel and efficient coarsening and refinement heuristics. The quality of the computed acyclic partitions is assessed by computing the edge cut. We also propose effective ways to use the standard undirected graph partitioning methods in our multilevel scheme. We perform a large set of experiments on a dataset consisting of (i) graphs coming from an application and (ii) some others corresponding to matrices from a public collection. We report improvements, on average, around 59% compared to the current state of the art

Modèle de placement pour les architectures nano-composantes

RÉSUMÉ Depuis la création de l’industrie des transistors CMOS, on assiste à un développement sans précédent de la miniaturisation. L’ITRS prévoit la limite des technologies basées sur le CMOS en 2020. Dans ce contexte, apparait de nouvelles disciplines, au coeur de la nanotechnologie, qui permettent de définir de nouvelles technologies permettant de compléter et/ou remplacer les transistors CMOS. Ces nouveaux transistors ouvrent la voie vers un nouveau paradigme d’architectures nano-composantes. Ces architectures ont trois principales caractéristiques : Les cellules logiques sont dynamiquement reconfigurables. Ce qui donne la possibilité d’exécuter en pipeline plusieurs fonctions différentes; La granularité est très fine. Ceci impose de considérer l’extensibilité des outils qui permettront l’exploitation de ces architectures; Elles ont une structure hiérarchique particulière : Dans les architectures nano-composantes les cellules logiques sont organisées en matrices avec des connexions statiques et les matrices en réseau de matrices avec des connexions dynamiques. Ces architectures peuvent alors être paramétrées en fonction de la taille des matrices (nombre de cellules) et de la taille du réseau (nombre de matrices). Pour prouver l’efficacité des architectures nano-composantes, il va falloir envisager la réalisation physique de systèmes complexes très performants basés sur ces technologies ainsi que l’utilisation des ces nano-systèmes. Comme l’accès au prototypage est très difficile et qu’il est souhaitable de réduire le temps de production des systèmes, la définition de nouveaux outils de conception assistée par ordinateur (CAO) s’avère nécessaire. Plusieurs outils CAO permettant la définition de systèmes basés sur les architectures conventionnelles existent. Cependant, ces outils ne prennent pas en compte les caractéristiques des architectures nano-composantes.----------ABSTRACT International Technology Roadmap for Semiconductors (ITRS) predicts that CMOS devices will reach their limits in 2022. Consequently, new devices and more efficient technologies are required. In this context, many efforts have been made to extend or replace conventional, CMOS devices. Some devices based on Field Effect Transistor (FET) nanotechnology such as the Dual Gate Carbon NanoTube FET (DG-CNTFET), the Nano Wire FET (NWFET) or the Grapheme FET (GFET) are promising candidates to replace CMOS devices. They lead to define new paradigm of non-conventional architectures (so called nano-component architecture). Nano-component architectures have three main characteristics: The logic cells are dynamically reconfigurable. This characteristic allows performing pipeline on several different functions; The granularity is ultra-fine (at most 2-bit operation). This characteristic implies to take into consideration scalability to exploit those architectures; The logic cells are organized with hierarchical structure and connectivity restrictions. In this structure, cells are organized in matrix and the matrices are organized in cluster. Exploiting those characteristics, nano–architecture are expected, compared to conventional architectures, to reduce the area and the cost and to improve the performance of a broad range of applications. In order to explore the potential of nano-architecture, new CAD tools are required. Those tools must take into account many parameters in nano-architecture definition: the number of cell in matrices, the number of matrices in cluster, the hierarchical structure, the connectivity restrictions, the fine granularity, the high reconfiguration, the pipeline and parallel execution… Although many CAD tools defined for conventional architecture have been proposed, they do not take into consideration nano-architecture parameters

Acyclic Multi-Way Partitioning of Boolean Networks

Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we present two efficient algorithms for the acyclic multi-way partitioning. One is a generalized FMbased algorithm. The other is based on the theory of maximum fanout-free cone (MFFC) decomposition. The acyclic FM-algorithm usually results in larger cut-size, as expected, compared to the undirected FM-algorithm due to the acyclic constraint. To our surprise, however, the MFFC-based acyclic partitioning algorithm consistently produces smaller (50% on average) cut-sized solutions than the conventional FM-algorithm. This result suggests that considering signal directions during the process can lead to very natural circuit decomposition and clustering, which in turn results in better partitioning solutions. We have also implemented parallel gate level simulators in Maisie and applied our partitioning algorithms to evaluat..

Acyclic Multi-Way Partitioning of Boolean Networks

Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we present two efficient algorithms for the acyclic multi-way partitioning. One is a generalized FMbased algorithm. The other is based on the theory of maximum fanout-free cone (MFFC) decomposition. The acyclic FM-algorithm usually results in larger cut-size, as expected, compared to the undirected FM-algorithm due to the acyclic constraint. To our surprise, however, the MFFC-based acyclic partitioning algorithm consistently produces smaller (50% on average) cut-sized solutions than the conventional FM-algorithm. This result suggests that considering signal directions during the process can lead to very natural circuit decomposition and clustering, which in turn results in better partitioning solutions. We have also implemented parallel gate level simulators in Maisie and applied our partitioning algorithms to evaluate their impact on circuit simulation