Leakage Power Minimization Using Gating Technique In FPGA Controlled Device

FPGA based controlled devices are widely used in integrated chip sector provided the power consumed by such devices should be low. Leakage power takes vital part in contributing towards the total power consumption. This research work concentrates in proposing a power gating technique based on look up table approach. The novelty of this approach is that common look up tables are employed for asynchronous architectures for each leaf node. Due to this the leakage power and the total area overhead can be minimized. The proposed architecture is simulated through M-Power analysis and simulator tool for leaf nodes and efficiently utilizes H-tree methodology to minimize area. The reduction in number of look up tables leads to 45% to 50% reduction in leakage power of FPGA device

Digital Single Phase Power Factor Optimizer Based on FPGA

In this paper, an FPGA (Field-programmable gate array) model of digital single phase power factor optimizer has been built. The proposed optimizer is based on measuring the phase shift time between voltage and current waveforms. Therefore, it is required to reduce this time to make the voltage and current waves in phase as possible. Thus, the power factor will be in maximum value (closed to unity). The process of improving the power factor is carried out by connecting a set of capacitors in parallel with the load. The proposed power factor optimizer has been built using VHDL (Very high speed integrated circuit Hardware Description Language), simulated using Xilinx ISE 9.2i package and implemented using Spartan-3A XC3S700A FPGA kit. Implementation and Simulation behavioral model results show that the proposed optimizer satisfies the specified operational requirements and reflected impressive results when applied to different loads

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

The design of low-power SRAM cell becomes a necessity in today\u27s FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAM-based FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA

Circuit designs for low-power and SEU-hardened systems

The desire to have smaller and faster portable devices is one of the primary motivations for technology scaling. Though advancements in device physics are moving at a very good pace, they might not be aggressive enough for now-a-day technology scaling trends. As a result, the MOS devices used for present day integrated circuits are pushed to the limit in terms of performance, power consumption and robustness, which are the most critical criteria for almost all applications. Secondly, technology advancements have led to design of complex chips with increasing chip densities and higher operating speeds. The design of such high performance complex chips (microprocessors, digital signal processors, etc) has massively increased the power dissipation and, as a result, the operating temperatures of these integrated circuits. In addition, due to the aggressive technology scaling the heat withstanding capabilities of the circuits is reducing, thereby increasing the cost of packaging and heat sink units. This led to the increase in prominence for smarter and more robust low-power circuit and system designs. Apart from power consumption, another criterion affected by technology scaling is robustness of the design, particularly for critical applications (security, medical, finance, etc). Thus, the need for error free or error immune designs. Until recently, radiation effects were a major concern in space applications only. With technology scaling reaching nanometer level, terrestrial radiation has become a growing concern. As a result Single Event Upsets (SEUs) have become a major challenge to robust designs. Single event upset is a temporary change in the state of a device due to a particle strike (usually from the radiation belts or from cosmic rays) which may manifest as an error at the output. This thesis proposes a novel method for adaptive digital designs to efficiently work with the lowest possible power consumption. This new technique improves options in performance, robustness and power. The thesis also proposes a new dual data rate flipflop, which reduces the necessary clock speed by half, drastically reducing the power consumption. This new dual data rate flip-flop design culminates in a proposed unique radiation hardened dual data rate flip-flop, Firebird\u27. Firebird offers a valuable addition to the future circuit designs, especially with the increasing importance of the Single Event Upsets (SEUs) and power dissipation with technology scaling.\u2

Profile-directed specialisation of custom floating-point hardware

We present a methodology for generating floating-point arithmetic hardware designs which are, for suitable applications, much reduced in size, while still retaining performance and IEEE-754 compliance. Our system uses three key parts: a profiling tool, a set of customisable floating-point units and a selection of system integration methods. We use a profiling tool for floating-point behaviour to identify arithmetic operations where fundamental elements of IEEE-754 floating-point may be compromised, without generating erroneous results in the common case. In the uncommon case, we use simple detection logic to determine when operands lie outside the range of capabilities of the optimised hardware. Out-of-range operations are handled by a separate, fully capable, floatingpoint implementation, either on-chip or by returning calculations to a host processor. We present methods of system integration to achieve this errorcorrection. Thus the system suffers no compromise in IEEE-754 compliance, even when the synthesised hardware would generate erroneous results. In particular, we identify from input operands the shift amounts required for input operand alignment and post-operation normalisation. For operations where these are small, we synthesise hardware with reduced-size barrel-shifters. We also propose optimisations to take advantage of other profile-exposed behaviours, including removing the hardware required to swap operands in a floating-point adder or subtractor, and reducing the exponent range to fit observed values. We present profiling results for a range of applications, including a selection of computational science programs, Spec FP 95 benchmarks and the FFMPEG media processing tool, indicating which would be amenable to our method. Selected applications which demonstrate potential for optimisation are then taken through to a hardware implementation. We show up to a 45% decrease in hardware size for a floating-point datapath, with a correctable error-rate of less then 3%, even with non-profiled datasets

Técnicas de bajo consumo en FPGAs

Todo diseño electrónico tiene tres restricciones principales que son área, velocidad y consumo. De las tres, el consumo es la variable más complicada de manejar para un diseñador: tiene incertidumbres, es difícil de estimar, y depende de varios parámetros, algunos tan dispares como el funcionamiento del sistema o los datos que ingresan al mismo. Pero por otro lado el consumo se está volviendo la restricción más importante para un gran número de aplicaciones. En esta tesis se presentan una serie de herramientas y metodologías para poder manejar adecuadamente la variable consumo en FPGAs. Se trabaja con un enfoque fuertemente experimental y desde el punto de vista de un usuario de este tipo de dispositivos, validando los resultados con más de 350 experimentos. Uno de los aportes de esta tesis, es una metodología completa de medición de consumo para FPGAs, que permite la calibración de herramientas de estimación. Como parte de esta metodología se incluyen los circuitos eléctricos necesarios para realizar las medidas y un conjunto de diseños o benchmarks para realizar pruebas incluyendo generadores de vectores de entradas. Se desarrolla además una herramienta específica de automedida de consumo para FPGAs. La misma tiene varias aplicaciones que permitirán ampliar y mejorar los experimentos de bajo consumo en futuras investigaciones, usando recursos muy sencillos y de muy bajo costo. Se presentan una serie de experimentos con varias técnicas de reducción de consumo en FPGAs, y se cuantifican los resultados obtenidos con cada una de ellas. Finalmente se concluye con un caso de estudio, la reducción de consumo de un circuito en particular: el microcontrolador openMSP430

Leakage Power Modeling and Reduction Techniques for Field Programmable Gate Arrays

FPGAs have become quite popular for implementing digital circuits and systems because of reduced costs and fast design cycles. This has led to increased complexity of FPGAs, and with technology scaling, many new challenges have come up for the FPGA industry, leakage power being one of the key challenges. The current generation FPGAs are being implemented in 90nm technology, therefore, managing leakage power in deep-submicron FPGAs has become critical for the FPGA industry to remain competitive in the semiconductor market and to enter the mobile applications domain. In this work an analytical state dependent leakage power model for FPGAs is developed, followed by dual-Vt based designs of the FPGA architecture for reducing leakage power. The leakage power model computes subthreshold and gate leakage in FPGAs, since these are the two dominant components of total leakage power in the scaled nanometer technologies. The leakage power model takes into account the dependency of gate and subthreshold leakage on the state of the circuit inputs. The leakage power model has two main components, one which computes the probability of a state for a particular FPGA circuit element, and the other which computes the leakage of the FPGA circuit element for a given input using analytical equations. This FPGA power model is particularly important for rapidly analyzing various FPGA architectures across different technology nodes. Dual-Vt based designs of the FPGA architecture are proposed, developed, and evaluated, for reducing the leakage power using a CAD framework. The logic and the routing resources of the FPGA are considered for dual-Vt assignment. The number of the logic elements that can be assigned high-Vt in the ideal case by using a dual-Vt assignment algorithm in the CAD framework is estimated. Based upon this estimate two kinds of architectures are developed and evaluated, homogeneous and heterogeneous architectures. Results indicate that leakage power savings of up to 50% can be obtained from these architectures. The analytical state dependent leakage power model developed has been used for estimating the leakage power savings from the dual-Vt FPGA architectures. The CAD framework that has been developed can also be used for developing and evaluating different dual-Vt FPGA architectures, other than the ones proposed in this work

ReSCon '09, Research Student Conference: Book of Abstracts

The second SED Research Student Conference (ReSCon2009) was hosted over three days, 22-24 June 2009, in the Lecture Centre at Brunel University. The conference consisted of technical presentations, a poster session and social events. The abstracts and presentations were the result of ongoing research by postgraduate research students from the School of Engineering and Design at Brunel University. The conference is held annually, and ReSCon plays a key role in contributing to research and innovations within the School

Estimación estadística de consumo en FPGAs

Tesis doctoral inédita. Universidad Autónoma de Madrid, Escuela Politécnica Superior, junio de 200