Software maintenance: generating front ends for cross referencer tools

This thesis surveys the activities performed in software maintenance and identifies some of the software tools which can be utilised by the maintenance programmer. The most expensive phase of software maintenance is surveyed in more detail and tools to support this activity are identified. A new class of cross referencer tool was designed and investigated. The novel aspect of the cross referencer is that it can be used on more than one language, by utihzing grammar driven generators to customize and make maximum re-use of the language independent components, allowing language specific implementations to be generated with minimal effort. The cross referencer also extends an idea of having different levels of detail in cross reference listings by allowing the tool implementor to specify the contents of each level of detail. A proposed experimental toolkit for the automatic construction of these cross referencer front end tools, from non procedural specifications, is designed and investigated

A survey of compiler development aids

A theoretical background was established for the compilation process by dividing it into five phases and explaining the concepts and algorithms that underpin each. The five selected phases were lexical analysis, syntax analysis, semantic analysis, optimization, and code generation. Graph theoretical optimization techniques were presented, and approaches to code generation were described for both one-pass and multipass compilation environments. Following the initial tutorial sections, more than 20 tools that were developed to aid in the process of writing compilers were surveyed. Eight of the more recent compiler development aids were selected for special attention - SIMCMP/STAGE2, LANG-PAK, COGENT, XPL, AED, CWIC, LIS, and JOCIT. The impact of compiler development aids were assessed some of their shortcomings and some of the areas of research currently in progress were inspected

Automatic Generation of Data Conversions - Programs Using a Data Description Language (DDL) Volume 1 and 2

The report describes a DDL/DML Processor and a methodology to automatically generate data conversion programs. The Processor, accepts as input descriptions of source and target files in a Data Description Language (DDL) and a Data Manipulation Language (DML). It produces an output conversion program in PL/l capable of converting the source file and producing the target file

FTMP (Fault Tolerant Multiprocessor) programmer's manual

The Fault Tolerant Multiprocessor (FTMP) computer system was constructed using the Rockwell/Collins CAPS-6 processor. It is installed in the Avionics Integration Research Laboratory (AIRLAB) of NASA Langley Research Center. It is hosted by AIRLAB's System 10, a VAX 11/750, for the loading of programs and experimentation. The FTMP support software includes a cross compiler for a high level language called Automated Engineering Design (AED) System, an assembler for the CAPS-6 processor assembly language, and a linker. Access to this support software is through an automated remote access facility on the VAX which relieves the user of the burden of learning how to use the IBM 4381. This manual is a compilation of information about the FTMP support environment. It explains the FTMP software and support environment along many of the finer points of running programs on FTMP. This will be helpful to the researcher trying to run an experiment on FTMP and even to the person probing FTMP with fault injections. Much of the information in this manual can be found in other sources; we are only attempting to bring together the basic points in a single source. If the reader should need points clarified, there is a list of support documentation in the back of this manual

Avionics architecture studies for the entry research vehicle

This report is the culmination of a year-long investigation of the avionics architecture for NASA's Entry Research Vehicle (ERV). The Entry Research Vehicle is conceived to be an unmanned, autonomous spacecraft to be deployed from the Shuttle. It will perform various aerodynamic and propulsive maneuvers in orbit and land at Edwards AFB after a 5 to 10 hour mission. The design and analysis of the vehicle's avionics architecture are detailed here. The architecture consists of a central triply redundant ultra-reliable fault tolerant processor attached to three replicated and distributed MIL-STD-1553 buses for input and output. The reliability analysis is detailed here. The architecture was found to be sufficiently reliable for the ERV mission plan