A GHz-range, High-resolution Multi-modulus Prescaler for Extreme Environment Applications

The generation of a precise, low-noise, reliable clock source is critical to developing mixed-signal and digital electronic systems. The applications of such a clock source are greatly expanded if the clock source can be configured to output different clock frequencies. The phase-locked loop (PLL) is a well-documented architecture for realizing this configurable clock source. Principle to the configurability of a PLL is a multi-modulus divider. The resolution of this divider (or prescaler) dictates the resolution of the configurable PLL output frequency. In integrated PLL designs, such a multi-modulus prescaler is usually sourced from a GHz-range voltage-controlled oscillator. Therefore, a fully-integrated PLL ASIC requires the development of a high-speed, high-resolution multi-modulus prescaler. The design challenges associated with developing such a prescaler are compounded when the application requires the device to operate in an extreme environment. In these extreme environments (often extra-terrestrial), wide temperature ranges and radiation effects can adversely affect the operation of electronic systems. Even more problematic is that extreme temperatures and ionizing radiation can cause permanent damage to electronic devices. Typical commercial-off-the-shelf (COTS) components are not able withstand such an environment, and any electronics operating in these extreme conditions must be designed to accommodate such operation. This dissertation describes the development of a high-speed, high-resolution, multi-modulus prescaler capable of operating in an extreme environment. This prescaler has been developed using current-mode logic (CML) on a 180-nm silicon-germanium (SiGe) BiCMOS process. The prescaler is capable of operating up to at least 5.4 GHz over a division range of 16-48 with a total of 27 configurable moduli. The prescaler is designed to provide excellent ionizing radiation hardness, single-event latch-up (SEL) immunity, and single-event upset (SEU) resistance over a temperature range of −180°C to 125°C

CMOS dual-modulus prescaler design for RF frequency synthesizer applications.

Ng Chong Chon.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 100-103).Abstract in English and Chinese.摘要 --- p.iiiAcknowledgments --- p.ivContents --- p.viList of Figures --- p.ixList of Tables --- p.xiiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Thesis Organization --- p.4Chapter Chapter 2 --- DMP Architecture --- p.6Chapter 2.1 --- Conventional DMP --- p.6Chapter 2.1.1 --- Operating Principle --- p.7Chapter 2.1.2 --- Disadvantages --- p.10Chapter 2.2 --- Pre-processing Clock Architecture --- p.10Chapter 2.2.1 --- Operating Principle --- p.11Chapter 2.2.2 --- Advantages and Disadvantages --- p.12Chapter 2.3 --- Phase-switching Architecture --- p.13Chapter 2.3.1 --- Operating Principle --- p.13Chapter 2.3.2 --- Advantages and Disadvantages --- p.14Chapter 2.4 --- Summary --- p.15Chapter Chapter 3 --- Full-Speed Divider Design --- p.16Chapter 3.1 --- Introduction --- p.16Chapter 3.2 --- Working Principle --- p.16Chapter 3.3 --- Design Issues --- p.18Chapter 3.4 --- Device Sizing --- p.19Chapter 3.5 --- Layout Considerations --- p.20Chapter 3.6 --- Input Sensitivity --- p.22Chapter 3.7 --- Modeling --- p.24Chapter 3.8 --- Review on Different Divider Designs --- p.28Chapter 3.8.1 --- Divider with Dynamic-Loading Technique --- p.28Chapter 3.8.2 --- Divider with Negative-Slew Technique --- p.30Chapter 3.8.3 --- LC Injection-Locked Frequency Divider --- p.32Chapter 3.8.4 --- Dynamic True Single Phase Clock Frequency Divider --- p.34Chapter 3.9 --- Summary --- p.42Chapter Chapter 4 --- 3V 900MHz Low Noise DMP --- p.43Chapter 4.1 --- Introduction --- p.43Chapter 4.2 --- Proposed DMP Topology --- p.46Chapter 4.3 --- Circuit Design and Implementation --- p.49Chapter 4.4 --- Simulation Results --- p.51Chapter 4.5 --- Summary --- p.53Chapter Chapter 5 --- 1.5V 2.4GHz Low Power DMP --- p.54Chapter 5.1 --- Introduction --- p.54Chapter 5.2 --- Proposed DMP Topology --- p.56Chapter 5.3 --- Circuit Design and Implementation --- p.59Chapter 5.3.1 --- Divide-by-4 stage --- p.59Chapter 5.3.2 --- TSPC dividers --- p.63Chapter 5.3.3 --- Phase-selection Network --- p.63Chapter 5.3.4 --- Mode-control Logic --- p.64Chapter 5.3.5 --- Duty-cycle Transformer --- p.65Chapter 5.3.6 --- Glitch Problem --- p.66Chapter 5.3.7 --- Phase-mismatch Problem --- p.70Chapter 5.4 --- Simulation Results --- p.70Chapter 5.5 --- Summary --- p.74Chapter Chapter 6 --- 1.5V 2.4GHz Wideband DMP --- p.75Chapter 6.1 --- Introduction --- p.75Chapter 6.2 --- Proposed DMP Architecture --- p.75Chapter 6.3 --- Divide-by-4 Stage --- p.76Chapter 6.3.1 --- Current-switch Combining --- p.76Chapter 6.3.2 --- Capacitive Load Reduction --- p.77Chapter 6.4 --- Simulation Results --- p.81Chapter 6.5 --- Summary --- p.83Chapter Chapter 7 --- Experimental Results --- p.84Chapter 7.1 --- Introduction --- p.84Chapter 7.2 --- Equipment Setup --- p.84Chapter 7.3 --- Measurement Results --- p.85Chapter 7.3.1 --- 3V 900GHz Low Noise DMP --- p.85Chapter 7.3.2 --- 1.5V 2.4GHz Low Power DMP --- p.88Chapter 7.3.3 --- 1.5V 2.4GHz Wideband DMP --- p.93Chapter 7.3 --- Summary --- p.96Chapter Chapter 8 --- Conclusions and Future Works --- p.98Chapter 8.1 --- Conclusions --- p.98Chapter 8.2 --- Future Works --- p.99References --- p.100Publications --- p.10

Process and Temperature Compensated Wideband Injection Locked Frequency Dividers and their Application to Low-Power 2.4-GHz Frequency Synthesizers

There has been a dramatic increase in wireless awareness among the user community in the past five years. The 2.4-GHz Industrial, Scientific and Medical (ISM) band is being used for a diverse range of applications due to the following reasons. It is the only unlicensed band approved worldwide and it offers more bandwidth and supports higher data rates compared to the 915-MHz ISM band. The power consumption of devices utilizing the 2.4-GHz band is much lower compared to the 5.2-GHz ISM band. Protocols like Bluetooth and Zigbee that utilize the 2.4-GHz ISM band are becoming extremely popular. Bluetooth is an economic wireless solution for short range connectivity between PC, cell phones, PDAs, Laptops etc. The Zigbee protocol is a wireless technology that was developed as an open global standard to address the unique needs of low-cost, lowpower, wireless sensor networks. Wireless sensor networks are becoming ubiquitous, especially after the recent terrorist activities. Sensors are employed in strategic locations for real-time environmental monitoring, where they collect and transmit data frequently to a nearby terminal. The devices operating in this band are usually compact and battery powered. To enhance battery life and avoid the cumbersome task of battery replacement, the devices used should consume extremely low power. Also, to meet the growing demands cost and sized has to be kept low which mandates fully monolithic implementation using low cost process. CMOS process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. A fully integrated solution is attractive for low power consumption as it avoids the need for power hungry drivers for driving off-chip components. The transceiver is often the most power hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator in the transmitter’s frequency synthesizer are among the major sources of power consumption. There have been a number of publications in the past few decades on low-power high-performance VCOs. Therefore this work focuses on prescalers. A class of analog frequency dividers called as Injection-Locked Frequency Dividers (ILFD) was introduced in the recent past as low power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However the range of operation frequency also knows as the locking range is limited. ILFDs can be classified as LC based and Ring based. Though LC based are insensitive to process and temperature variation, they cannot be used for the 2.4-GHz ISM band because of the large size of on-chip inductors at these frequencies. This causes a lot of valuable chip area to be wasted. Ring based ILFDs are compact and provide a low power solution but are extremely sensitive to process and temperature variations. Process and temperature variation can cause ring based ILFD to loose lock in the desired operating band. The goal of this work is to make the ring based ILFDs useful for practical applications. Techniques to extend the locking range of the ILFDs are discussed. A novel and simple compensation technique is devised to compensate the ILFD and keep the locking range tight with process and temperature variations. The proposed ILFD is used in a 2.4-GHz frequency synthesizer that is optimized for fractional-N synthesis. Measurement results supporting the theory are provided

A high-frequency quad-modulus prescaler for fractional-N frequency synthesizer

Master'sMASTER OF ENGINEERIN

A low phase noise ring oscillator phase-locked loop for wireless applications

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 129).This thesis describes the circuit level design of a 900MHz [Sigma][Detta] ring oscillator based phase-locked loop using 0.35[mu]m technology. Multiple phase noise theories are considered giving insight into low phase-noise voltage controlled oscillator design. The circuit utilizes a fully symmetric differential voltage controlled oscillator with cascode current starved inverters to reduces current noise. A compact multi-modulus prescaler is presented, based on modified true single-phase clock flip-flops with integrated logic. A fully differential charge pump with switched-capacitor common mode feedback is utilized in conjunction with a nonlinear phase-frequency detector for accelerated acquisition time.by Colin Weltin-Wu.M.Eng

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range

Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range

Design and implementation of intravascular hifu catheter ablation system

High-intensity focused ultrasound is an energy-based thermal therapy for noninvasive or minimally invasive treatment of wide range of medical disorders including solid cancer tumors, brain surgery, atrial fibrillation (AF) and other cardiac arrhythmias. Conventional HIFU is extracorporeally administered but in applications where a small lesion or more precise energy localization in shorter time is required, catheter-based HIFU devices which are positioned directly within or adjacent to the target may be the best solution. Available HIFU catheters use array of piezoelectric transducers with complex external high-voltage (HV) and high-frequency amplifiers, a cooling system and several coaxial cables within the catheter. In this study, a HV transmitter IC has been designed, manufactured and integrated with an 8-element capacitive micromachined ultrasound transducer (CMUT) on a prototype HIFU probe appropriate for a 6-Fr catheter. The transmitter IC fabricated in 0.35 μm HV CMOS process and comprises eight continuouswave HV buffers (10.9 ns and 9.4 ns rise and fall times at 20 Vpp output into a 15 pF), an eight-channel transmit beamformer (8-12 MHz output frequency with 11.25 º phase accuracy) and a phase locked loop with an integrated VCO as a tunable clock source (128–192 MHz). The chip occupies 1.85×1.8 mm2 area including input and output (I/O) pads. Electrical measurements, IR thermography and Ex-vivo experiment results reveal that the presented HIFU system can elevate the temperature of the target region of tissue around 19 ºC by delivering 600 CEM43 equivalent thermal dose while surface temperature of the probe rises less than 5 º

Synthèse de fréquence multi-bandes couvrant les ondes millimétriques pour les applications WiFi-WiGig

The works presented in this manuscript focus on the realization of a millimeter frequency synthesizer meeting the needs of the WiGig-Fi convergence. A first study was conducted to define a suitable low-power frequency synthesizer archi-tecture for WiFi and WiGig standards. All of the PLL components are subsequently detailed, highlighting the 28nm CMOS FDSOI technology benefits. Then, a study of low power millimeter broadband VCO is presented, highlighting a design methodology related to the 28nm CMOS FDSOI technology. Finally, various solutions are proposed in order to improve the PLL performances, with the incorporation of slow wave VCO, or injection locked ring oscillators.L’ensemble des travaux présentés au sein de manuscrit porte sur la réalisation d’un synthétiseur de fréquences millimétriques capable de répondre aux besoins de la convergence WiFi-WiGig. Une première étude est réalisée dans le but de définir une architecture de synthétiseur de fréquence faible consommation adaptée aux standards du WiFi et du WiGig. L’ensemble des éléments composants la PLL sont par la suite détaillés, mettant en avant les avantages offerts par la technologie 28 nm FDSOI CMOS. Une étude plus approfondie des VCO millimétriques large bande et faible consommation est ensuite présentée, permettant de mettre en avant une réelle méthodologie de conception en lien avec la technologie 28 nm FDSOI CMOS. Finale-ment, diverses solutions sont proposées dans le but d’améliorer les performances de la PLL, avec l’incorporation de VCO millimétriques à ondes lentes, ou d’oscillateurs à anneaux synchronisés