Analyses and design strategies for fundamental enabling building blocks: Dynamic comparators, voltage references and on-die temperature sensors

Dynamic comparators and voltage references are among the most widely used fundamental building blocks for various types of circuits and systems, such as data converters, PLLs, switching regulators, memories, and CPUs. As thermal constraints quickly emerged as a dominant performance limiter, on-die temperature sensors will be critical to the reliable operation of future integrated circuits. This dissertation investigates characteristics of these three enabling circuits and design strategies for improving their performances. One of the most critical specifications of a dynamic comparator is its input referred offset voltage, which is pivotal to achieving overall system performance requirements of many mixed-signal circuits and systems. Unlike offset voltages in other circuits such as amplifiers, the offset voltage in a dynamic comparator is extremely challenging to analyze and predict analytically due to its dependence on transient response and due to internal positive feedback and time-varying operating points in the comparator. In this work, a novel balanced method is proposed to facilitate the evaluation of time-varying operating points of transistors in a dynamic comparator. Two types of offsets are studied in the model: (1) static offset voltage caused by mismatches in mobilities, transistor sizes, and threshold voltages, and (2) dynamic offset voltage caused by mismatches in parasitic capacitors or loading capacitors. To validate the proposed method, dynamic comparators in two prevalent topologies are implemented in 0.25 μm and 40 nm CMOS technologies. Agreement between predicted results and simulated results verifies the effectiveness of the proposed method. The new method and the analytical models enable designers to identify the most dominant contributors to offset and to optimize the dynamic comparators\u27 performances. As an illustrating example, the Lewis-Gray dynamic comparator was analyzed using the balanced method and redesigned to minimize its offset voltage. Simulation results show that the offset voltage was easily reduced by 41% while maintaining the same silicon area. A bandgap voltage reference is one of the core functional blocks in both analog and digital systems. Despite the reported improvements in performance of voltage references, little attention has been focused on theoretical characterizations of non-ideal effects on the value of the output voltage, on the inflection point location and on the curvature of the reference voltage. In this work, a systematic approach is proposed to analytically determine the effects of two non-ideal elements: the temperature dependent gain-determining resistors and the amplifier offset voltage. The effectiveness of the analytical models is validated by comparing analytical results against Spectre simulation results. Research on on-die temperature sensor design has received rapidly increasing attention since component and power density induced thermal stress has become a critical factor in the reliable operation of integrated circuits. For effective power and thermal management of future multi-core systems, hundreds of sensors with sufficient accuracy, small area and low power are required on a single chip. This work introduces a new family of highly linear on chip temperature sensors. The proposed family of temperature sensors expresses CMOS threshold voltage as an output. The sensor output is independent of power supply voltage and independent of mobility values. It can achieve very high temperature linearity, with maximum nonlinearity around +/- 0.05oC over a temperature range of -20oC to 100oC. A sizing strategy based on combined analytical analysis and numerical optimization has been presented. Following this method, three circuits A, B and C have been designed in standard 0.18 ym CMOS technology, all achieving excellent linearity as demonstrated by Cadence Spectre simulations. Circuits B and C are the modified versions of circuit A, and have improved performance at the worst corner-low voltage supply and high threshold voltage corner. Finally, a direct temperature-to-digital converter architecture is proposed as a master-slave hybrid temperature-to-digital converter. It does not require any traditional constant reference voltage or reference current, it does not attempt to make any node voltage or branch current constant or precisely linear to temperature, yet it generates a digital output code that is very linear with temperature

Fast, non-monte-carlo estimation of transient performance variation due to device mismatch

This paper describes an efficient way of simulating the effects of device random mismatch on circuit transient characteristics, such as variations in delay or in frequency. The proposed method models DC random offsets as equivalent AC pseudo-noises and leverages the fast, linear periodically time-varying (LPTV) noise analysis available from RF circuit simulators. Therefore, the method can be considered as an extension to DC match analysis and offers a large speed-up compared to the traditional Monte-Carlo analysis. Although the assumed linear perturbation model is valid only for small variations, it enables easy ways to estimate correlations among variations and identify the most sensitive design parameters to mismatch, all at no additional simulation cost. Three benchmarks measuring the variations in the input offset voltage of a clocked comparator, the delay of a logic path, and the frequency of an oscillator demonstrate the speed improvement of about 100-1000x compared to a 1000-point Monte-Carlo method

A low offset dynamic comparator with morphing amplifier

Dynamic comparators are popular structures used in analog circuits such as RFID tags, ADC, memory modules, etc. Compared with traditional open-loop amplifiers that can be used as a comparator, well-designed dynamic comparators are usually faster and more power-efficient, but dynamic CMPs also have some problems. Device mismatch-induced offset voltages is a major challenge when designing dynamic comparators because device mismatch is a random variable that is non-predictable during the design stage. There are many popular dynamic CMP structures; one of them is the Lewis-Gray dynamic comparator [1]. Many authors have introduced alternative dynamic comparator structures which they claim are less affected by device mismatch than the Lewis-Gray circuit but few present a comprehensive and reasonable comparison method. In those papers, different modifications are implemented in order to minimize device mismatch offset, one popular way is to add an amplifier stage before the dynamic comparator. The input signals are amplified in the first amplifier stage before going into the second dynamic comparator stage. Since the outputs of the first stage have a larger difference comparing with the inputs, the offset requirement for the dynamic comparator is loosened. However, the offset still has room for improvement. In this work, a low offset dynamic comparator with morphing amplifier is proposed. It doesn’t have two independent stages. Instead, the amp is inherently integrated into a dynamic comparator, and it yields better offset performance. Moreover, a new fair and comprehensive offset comparison method is also introduced

An offset auto-calibration technique with cost-effective implementation for comparator and operational amplifier

Comparators are one of the most fundamental building blocks in all electronic systems involving analog and digital information. A comparator’s performance, or the accuracy of its output, is determined by the comparator’s offset voltage, which includes random offset and systematic offset. To guarantee the overall performance of an entire electronic system, offset-trimming techniques are often necessary to reduce inaccuracy. This study analyzes the offset errors in a representative comparator structure and describes an auto-calibration technique to systematically and significantly reducing the offset. The auto-calibration technique involves trimming of the comparator input transistor pair. Various trimming-switch structures are considered and compared, such as constant-sized drain switch (CDS), constant-sized gate switch (CGS), constant-sized source switch (CSS), binary-weighted source switch (BSS), and constant size split-source switch (SSS). The comparator and the offset auto-calibration circuits are designed using the GlobalFoundry 0.13μm process. Then an offset trimming algorithm, which is written on MATLAB, is applied to these circuits. Afterwards, the results are collected and analyzed. A comparison of linearity and trimming range (TR) achieved with different trimming switch structures is performed to demonstrate advantages and disadvantages of each switch scheme. The results are also plotted in a histogram to show the normal distribution of each scheme. Finally, offset cancellation technique is implemented in an operational amplifier (Op Amp) circuit with further analysis and comparison to prove the methodology

redicting dynamic specifications of ADCs with a low-quality digital input signal

A new method is presented to test dynamic parameters of Analogue-to-Digital Converters (ADC). A noisy and nonlinear pulse is applied as the test stimulus, which is suitable for a multi-site test environment. The dynamic parameters are predicted using a machine-learning-based approach. A training step is required in order to build the mapping function using alternate signatures and the conventional test parameters, all measured on a set of converters. As a result, for industrial testing, only a simple signature-based test is performed on the Devices-Under-Test (DUTs). The signature measurements are provided to the mapping function that is used to predict the conventional dynamic parameters. The method is validated by simulation on a 12-bit 80 Ms/s pipelined ADC with a pulse wave input signal of 3 LSB noise and 7-bit nonlinear rising and falling edges. The final results show that the estimated mean error is less than 4% of the full range of the dynamic specifications

Background Digital Calibration of Comparator Offsets in Pipeline ADCs

This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.Junta de Andalucía P09-TIC-5386Gobierno Español TEC2011-2830

Event Driven Tactile Sensors for Artificial Devices

Present-day robots are, to some extent, able to deal with high complexity and variability of the real-world environment. Their cognitive capabilities can be further enhanced, if they physically interact and explore the real-world objects. For this, the need for efficient tactile sensors is growing day after day in such a way are becoming more and more part of daily life devices especially in robotic applications for manipulation and safe interaction with the environment. In this thesis, we highlight the importance of touch sensing in humans and robots. Inspired by the biological systems, in the the first part, we merge between neuromorphic engineering and CMOS technology where the former is a eld of science that replicates what is biologically (neurons of the nervous system) inside humans into the circuit level. We explain the operation and then characterize different sensor circuits through simulation and experiment to propose finally new prototypes based on the achieved results. In the second part, we present a machine learning technique for detecting the direction and orientation of a sliding tip over a complete skin patch of the iCub robot. Through learning and online testing, the algorithm classies different trajectories across the skin patch. Through this part, we show the results of the considered algorithm with a future perspective to extend the work

Error modeling, self-calibration and design of pipelined analog to digital converters

Typescript (photocopy).As the field of signal processing accelerates toward the use of high performance digital techniques, there is a growing need for increasingly fast and accurate analog to digital converters. Three highly visible examples of this trend originated in the last decade. The advent of the compact disc revolutionized the way high-fidelity audio is stored, reproduced, recorded and processed. Digital communication links, fiber optic cables and in the near future ISDN networks (Integrated Services Digital Network) are steadily replacing major portions of telephone systems. Finally, video-conferencing, multi-media computing and currently emerging high definition television (HDTV) systems rely more and more on real-time digital data compression and image enhancing techniques. All these applications rely on analog to digital conversion. In the field of digital audio, the required conversion accuracy is high, but the conversion speed limited (16 bits, 2 x 20 kHz signal bandwidth). In the field of image processing, the required accuracy is less, but the data conversion speed high (8-10 bits, 5-20MHz bandwidth). New applications keep pushing for increasing conversion rates and simultaneously higher accuracies. This dissertation discusses new analog to digital converter architectures that could accomplish this. As a consequence of the trend towards digital processing, prominent analog designers throughout the world have engaged in very active research on the topic of data conversion. Unfortunately, literature has not always kept up. At the time of this writing, it seemed rather difficult to find detailed fundamental publications about analog to digital converter design. This dissertation represents a modest attempt to remedy this situation. It is hoped that anyone with a back-ground in analog design could go through this work and pick up the fundamentals of converter operation, as well as a number of more advanced design techniques