Implementation of ECC on FPGA using Scalable Architecture With equal Data and Key for WSN

Security of data transferred on the Wireless Sensor Network is of vital importance. In public key cryptography RSA algorithm has been used for a long time, but it does not meet the constraints of WSNs. Elliptic Curve Cryptography(ECC) has been employed recently because of its highest security for same length bit. ECC point multiplication operation is time consuming which affects the speed of encryption and decryption of data. Security in WSNs is addressed in our work, where a modified ECC is designed by performing the point multiplication using Montgomery multiplication technique that achieves considerable speed and with reduced area utilization. The ECC is first simulated on different FPGA devices, with key length 11, 112, 131 and 163 bits and the area-speed tradeoff is compared. ECC algorithm is implemented with software and hardware choosing Artix 7 XC7a100t-3csg324 FPGA which supports key lengths of 11, 112, 131 and 163 bits. When implemented on a Artix 7 FPGA, it completes 163 bit data encryption operation over GF(2163 ) in 1ms with the maximum frequency of 229MHz. The ECC algorithm is reconfigurable with low level to high level security with different bit key sizes. The proposed ECC algorithm modeled using VHDL and synthesized on Spartan 3 and 6, Virtex 4, 5 and 6 and Artix7 before the hardware implementation on Atrix 7. The design satisfies the needs of resource constrained devices by decreasing the encryption and decryption time to 1 ms with equal keylength and datasize, while device utilization is within 13%

Hardware Implementations of Scalable and Unified Elliptic Curve Cryptosystem Processors

As the amount of information exchanged through the network grows, so does the demand for increased security over the transmission of this information. As the growth of computers increased in the past few decades, more sophisticated methods of cryptography have been developed. One method of transmitting data securely over the network is by using symmetric-key cryptography. However, a drawback of symmetric-key cryptography is the need to exchange the shared key securely. One of the solutions is to use public-key cryptography. One of the modern public-key cryptography algorithms is called Elliptic Curve Cryptography (ECC). The advantage of ECC over some older algorithms is the smaller number of key sizes to provide a similar level of security. As a result, implementations of ECC are much faster and consume fewer resources. In order to achieve better performance, ECC operations are often offloaded onto hardware to alleviate the workload from the servers' processors. The most important and complex operation in ECC schemes is the elliptic curve point multiplication (ECPM). This thesis explores the implementation of hardware accelerators that offload the ECPM operation to hardware. These processors are referred to as ECC processors, or simply ECPs. This thesis targets the efficient hardware implementation of ECPs specifically for the 15 elliptic curves recommended by the National Institute of Standards and Technology (NIST). The main contribution of this thesis is the implementation of highly efficient hardware for scalable and unified finite field arithmetic units that are used in the design of ECPs. In this thesis, scalability refers to the processor's ability to support multiple key sizes without the need to reconfigure the hardware. By doing so, the hardware does not need to be redesigned for the server to handle different levels of security. Unified refers to the ability of the ECP to handle both prime and binary fields. The resultant designs are valuable to the research community and industry, as a single hardware device is able to handle a wide range of ECC operations efficiently and at high speeds. Thus, improving the ability of network servers to handle secure transaction more quickly and improve productivity at lower costs

Co-diseño Hardware/Software para Criptografía de Curva Elíptica sobre plataformas en chip heterogéneas

Recientemente ha aparecido en el mercado un nuevo tipo de sistemas en chip heterogéneos que incluyen un multiprocesador basado en procesadores ARM y una FPGA (hardware programable al que se pueden asignar aceleradores en tiempo de ejecución). El objetivo de este trabajo ha sido el analizar cómo sacar partido a estas plataformas en el campo de la criptografía asimétrica de curva elíptica analizando las distintas posibilidades de codiseño hardware/software y sus compromisos entre coste y eficiencia. Se han utilizado dos de los algoritmos criptográficos más representativos y eficientes en entornos embebidos: la multiplicación de Montgomery sobre coordenadas proyectivas y la multiplicación de Frobenius sobre curvas Koblitz. Posteriormente se ha analizado el software para determinar las partes más adecuadas para ser sustituidas por un acelerador hardware implementado en la FPGA. Resultando las operaciones más costosas las de aritmética sobre cuerpos finitos (Multiplicación, división e inversión). Se ha demostrado posteriormente la escalabilidad de nuestro desarrollo implementando los algoritmos tanto sobre cuerpos GF(2^163) como GF(2^233). Cuerpos recomendados por el NIST (National Institute of Standards an Technology) y el SECG para aplicaciones en criptosistemas de curva elíptica. Se han desarrollado los aceleradores hardware en la parte de la lógica programable proporcionada por la plataforma en forma de dispositivos con registros accesibles y direccionables desde el software. La aritmética modular en hardware es de sobra conocida y en este trabajo se han desarrollado e integrado componentes ampliamente utilizados. Y Finalmente se han conseguido aceleraciones muy importantes, mientas que el consumo medio se ha mantenido, incluso disminuyéndose ligeramente, con lo que el ahorro energético se multiplica. Siendo un aspecto crítico en los dispositivos embebidos y con restricciones tales como tarjetas inteligentes y dispositivos móviles

IMPLEMENTATION OF DOUBLE ENCRYPTION USING ELGAMAL AND KNAPSACK ALGORITHM ON FPGA FOR NODES IN WIRELESS SENSOR NETWORKS

The primary objective of this proposed work is to implement elliptical curve cryptography with matrix mapping techniques and knapsack algorithm for information encryption and decryption in nodes of Wireless Sensor Networks. In this paper through mapping method there is complication to guess the phrases as it does not show any regularity and knapsack algorithm avoids brute drive attack by growing confusions. The modules are integrated to perform matrix mapping, Knapsack encryption, knapsack decryption and de mapping. Verilog language is used for coding and simulation is completing on Xilinx ISE 13.4 and Spartan 6, Kintex 5 and Artix 7 FPGAs are used as the hardware. The complete crypto process is executed with frequency of 503.702 MHz. No Maximum combinational path delay is found in the implementation of modules. In comparison with previous works the area utilization in this work is very less, thus satisfying the resource constraints‟ of wireless sensor nodes

Implementations of Wireless and Wired Intelligent Systems for Healthcare with Focus on Diabetes and Ultrasound Applications

The research and implementations presented in this thesis focuses mainly on healthcare applications utilizing the wireless and wired communication and “Micro-Electro-Mechanical Systems” (MEMS) technologies, and secondly on security aspects. Chapters four and five presents new work in intelligent diabetes remote monitoring front-end system and into the corresponding new ultrasound simulator training systems. The motivation from the University of Sheffield of Electronic and Electrical Engineering Department and Sheffield Children Hospital with the partial grant scholarship from “Engineering and Physical Sciences Research Council” (EPSRC) for involvement in one “Collaborations for Leadership in Applied Health Research and Care” (CLAHRC) projects, was to improve the existing WithCare+ system and also the development of multiple new front-end solutions for it. My motivation to create solutions which will improve the life of patients who suffer from chronic disease such as type-1 diabetes, and also to provide new methods in management of that illness by clinicians and possible resulting annual government money saving, drives me to the successful result. From the other side, the motivation from the department of Neonatal in Sheffield Royal Hallamshire Hospital and the University of Sheffield of Electronic and Electrical Engineering Department drives me to the creation of a new, very low cost ultrasound simulation training system, using new components such as MEMS sensors. The hardware design and embedded source code was created in order to provide a ready library, for use by other projects, where 3D space orientation is required through exploitation of MEMS sensors and intelligent fusion filter algorithm. The third contribution affects the cryptographic aspects. The new implementation of fast and very efficient portable C code algorithm for t-adic NAF Key generation in ECC cryptographic principle for utilization of it with Koblitz curves presented in Appendix I

Trusted Computing für adaptive Automobilsteuergeräte im Umfeld der Inter-Fahrzeug-Kommunikation

Die vorliegende Arbeit beschäftigt sich mit der Sicherheit (Security) von Automobilelektronik, speziell der Kommunikation zwischen Fahrzeugen für Safety-Anwendungen. Hierzu wird die Absicherung der Kommunikation über digitale Signaturen betrachtet und eine prototypische Implementierung auf rekonfigurierbarer Hardware vorgestellt. Darüber hinaus wird die Absicherung der Kommunikationsplattform selbst über die Anwendung von Trusted Computing für rekonfigurierbare Systeme sichergestellt

Trusted Computing für adaptive Automobilsteuergeräte im Umfeld der Inter-Fahrzeug-Kommunikation

Die vorliegende Arbeit beschäftigt sich mit der Sicherheit (Security) von Automobilelektronik, speziell der Kommunikation zwischen Fahrzeugen für Safety-Anwendungen. Hierzu wird die Absicherung der Kommunikation über digitale Signaturen betrachtet und eine prototypische Implementierung auf rekonfigurierbarer Hardware vorgestellt. Darüber hinaus wird die Absicherung der Kommunikationsplattform selbst über die Anwendung von Trusted Computing für rekonfigurierbare Systeme sichergestellt