Analysis and design of sinusoidal quadrature RC-oscillators

Modern telecommunication equipment requires components that operate in many different frequency bands and support multiple communication standards, to cope with the growing demand for higher data rate. Also, a growing number of standards are adopting the use of spectrum efficient digital modulations, such as quadrature amplitude modulation (QAM) and orthogonal frequency division multiplexing (OFDM). These modulation schemes require accurate quadrature oscillators, which makes the quadrature oscillator a key block in modern radio frequency (RF) transceivers. The wide tuning range characteristics of inductorless quadrature oscillators make them natural candidates, despite their higher phase noise, in comparison with LC-oscillators. This thesis presents a detailed study of inductorless sinusoidal quadrature oscillators. Three quadrature oscillators are investigated: the active coupling RC-oscillator, the novel capacitive coupling RCoscillator, and the two-integrator oscillator. The thesis includes a detailed analysis of the Van der Pol oscillator (VDPO). This is used as a base model oscillator for the analysis of the coupled oscillators. Hence, the three oscillators are approximated by the VDPO. From the nonlinear Van der Pol equations, the oscillators’ key parameters are obtained. It is analysed first the case without component mismatches and then the case with mismatches. The research is focused on determining the impact of the components’ mismatches on the oscillator key parameters: frequency, amplitude-, and quadrature-errors. Furthermore, the minimization of the errors by adjusting the circuit parameters is addressed. A novel quadrature RC-oscillator using capacitive coupling is proposed. The advantages of using the capacitive coupling are that it is noiseless, requires a small area, and has low power dissipation. The equations of the oscillation amplitude, frequency, quadrature-error, and amplitude mismatch are derived. The theoretical results are confirmed by simulation and by measurement of two prototypes fabricated in 130 nm standard complementary metal-oxide-semiconductor (CMOS) technology. The measurements reveal that the power increase due to the coupling is marginal, leading to a figure-of-merit of -154.8 dBc/Hz. These results are consistent with the noiseless feature of this coupling and are comparable to those of the best state-of-the-art RC-oscillators, in the GHz range, but with the lowest power consumption (about 9 mW). The results for the three oscillators show that the amplitude- and the quadrature-errors are proportional to the component mismatches and inversely proportional to the coupling strength. Thus, increasing the coupling strength decreases both the amplitude- and quadrature-errors. With proper coupling strength, a quadrature error below 1° and amplitude imbalance below 1% are obtained. Furthermore, the simulations show that increasing the coupling strength reduces the phase noise. Hence, there is no trade-off between phase noise and quadrature error. In the twointegrator oscillator study, it was found that the quadrature error can be eliminated by adjusting the transconductances to compensate the capacitance mismatch. However, to obtain outputs in perfect quadrature one must allow some amplitude error

A Noise-Shifting Differential Colpitts VCO

A novel noise-shifting differential Colpitts VCO is presented. It uses current switching to lower phase noise by cyclostationary noise alignment and improve the start-up condition. A design strategy is also devised to enhance the phase noise performance of quadrature coupled oscillators. Two integrated VCOs are presented as design examples

Development of a Miniature Electrostatic Accelerometer /MESA/ for low g applications Summary report

Design, fabrication, and testing of miniature digital electrostatic accelerometer for low gravity measurements in spac

A closed-loop digitally controlled MEMS gyroscope with unconstrained Sigma-Delta force-feedback

In this paper, we describe the system architecture and prototype measurements of a MEMS gyroscope system with a resolution of 0.025 degrees/s/root Hz. The architecture makes extensive use of control loops, which are mostly in the digital domain. For the primary mode both the amplitude and the resonance frequency are tracked and controlled. The secondary mode readout is based on unconstrained Sigma Delta force-feedback, which does not require a compensation filter in the loop and thus allows more beneficial quantization noise shaping than prior designs of the same order. Due to the force-feedback, the gyroscope has ample dynamic range to correct the quadrature error in the digital domain. The largely digital setup also gives a lot of flexibility in characterization and testing, where system identification techniques have been used to characterize the sensors. This way, a parasitic direct electrical coupling between actuation and readout of the mass-spring systems was estimated and corrected in the digital domain. Special care is also given to the capacitive readout circuit, which operates in continuous time

Multi-Phase Sub-Sampling Fractional-N PLL with soft loop switching for fast robust locking

This paper presents a low phase noise sub-sampling PLL (SSPLL) with multi-phase outputs. Automatic soft switching between the sub-sampling phase loop and frequency loop is proposed to improve robustness against perturbations and interferences that may cause a traditional SSPLL to lose lock. A quadrature LC oscillator with capacitive phase interpolation network is employed to generate multi-phase outputs, which are further utilized to achieve fractional-N frequency synthesis. Implemented in a 130nm CMOS technology, the SSPLL chip is able to achieve a measured in-band phase noise of -120 dBc/Hz and a measured integrated jitter of 209 fs at 2.4 GHz, while consuming 27.2 mW with 16 output phases. The measured reference spur and fractional spur level is -72 dBc and -49 dBc, respectively

Integrated phased array systems in silicon

Silicon offers a new set of possibilities and challenges for RF, microwave, and millimeter-wave applications. While the high cutoff frequencies of the SiGe heterojunction bipolar transistors and the ever-shrinking feature sizes of MOSFETs hold a lot of promise, new design techniques need to be devised to deal with the realities of these technologies, such as low breakdown voltages, lossy substrates, low-Q passives, long interconnect parasitics, and high-frequency coupling issues. As an example of complete system integration in silicon, this paper presents the first fully integrated 24-GHz eight-element phased array receiver in 0.18-μm silicon-germanium and the first fully integrated 24-GHz four-element phased array transmitter with integrated power amplifiers in 0.18-μm CMOS. The transmitter and receiver are capable of beam forming and can be used for communication, ranging, positioning, and sensing applications

Design considerations for a monolithic, GaAs, dual-mode, QPSK/QASK, high-throughput rate transceiver

A monolithic, GaAs, dual mode, quadrature amplitude shift keying and quadrature phase shift keying transceiver with one and two billion bits per second data rate is being considered to achieve a low power, small and ultra high speed communication system for satellite as well as terrestrial purposes. Recent GaAs integrated circuit achievements are surveyed and their constituent device types are evaluated. Design considerations, on an elemental level, of the entire modem are further included for monolithic realization with practical fabrication techniques. Numerous device types, with practical monolithic compatability, are used in the design of functional blocks with sufficient performances for realization of the transceiver

Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range

Interface Circuit for a Multiple-Beam Tuning-Fork Gyroscope with High Quality Factors

This research work presents the design, theoretical analysis, fabrication, interface electronics, and experimental results of a Silicon-On-Insulator (SOI) based Multiple-Beam Tuning-Fork Gyroscope (MB-TFG). Based on a numerical model of Thermo-Elastic Damping (TED), a Multiple-Beam Tuning-Fork Structure (MB-TFS) is designed with high Quality factors (Qs) in its two operation modes. A comprehensive theoretical analysis of the MB-TFG design is conducted to relate the design parameters to its operation parameters and further performance parameters. In conjunction with a mask that defines the device through trenches to alleviate severe fabrication effect on anchor loss, a simple one-mask fabrication process is employed to implement this MB-TFG design on SOI wafers. The fabricated MB-TFGs are tested with PCB-level interface electronics and a thorough comparison between the experimental results and a theoretical analysis is conducted to verify the MB-TFG design and accurately interpret the measured performance. The highest measured Qs of the fabricated MB-TFGs in vacuum are 255,000 in the drive-mode and 103,000 in the sense-mode, at a frequency of 15.7kHz. Under a frequency difference of 4Hz between the two modes (operation frequency is 16.8kHz) and a drive-mode vibration amplitude of 3.0μm, the measured rate sensitivity is 80μVpp/°/s with an equivalent impedance of 6MΩ. The calculated overall rate resolution of this device is 0.37/°hr/√Hz, while the measured Angle Random Walk (ARW) and bias instability are 6.67°/\u27√hr and 95°/hr, respectively