Development of a character, line and point display system

A compact graphics terminal for use as the input to a computerized medical records system is described. The principal mode of communication between the terminal and the records system is by checklists and menu selection. However, the terminal accepts short, handwritten messages as well as conventional alphanumeric input. The terminal consists of an electronic tablet, a display, a microcomputer controller, a character generator, and a refresh memory for the display. An Intel SBC 80/10 microcomputer controls the flow of information and a 16 kilobyte memory stores the point-by-point array of information to be displayed. A specially designed interface continuously generates the raster display without the intervention of the microcomputer

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification

Modern Systems-on-Chip (SoC) designs are increasingly heterogeneous and contain specialized semi-programmable accelerators in addition to programmable processors. In contrast to the pre-accelerator era, when the ISA played an important role in verification by enabling a clean separation of concerns between software and hardware, verification of these "accelerator-rich" SoCs presents new challenges. From the perspective of hardware designers, there is a lack of a common framework for the formal functional specification of accelerator behavior. From the perspective of software developers, there exists no unified framework for reasoning about software/hardware interactions of programs that interact with accelerators. This paper addresses these challenges by providing a formal specification and high-level abstraction for accelerator functional behavior. It formalizes the concept of an Instruction Level Abstraction (ILA), developed informally in our previous work, and shows its application in modeling and verification of accelerators. This formal ILA extends the familiar notion of instructions to accelerators and provides a uniform, modular, and hierarchical abstraction for modeling software-visible behavior of both accelerators and programmable processors. We demonstrate the applicability of the ILA through several case studies of accelerators (for image processing, machine learning, and cryptography), and a general-purpose processor (RISC-V). We show how the ILA model facilitates equivalence checking between two ILAs, and between an ILA and its hardware finite-state machine (FSM) implementation. Further, this equivalence checking supports accelerator upgrades using the notion of ILA compatibility, similar to processor upgrades using ISA compatibility.Comment: 24 pages, 3 figures, 3 table

Comparative evaluation of approaches in T.4.1-4.3 and working definition of adaptive module

The goal of this deliverable is two-fold: (1) to present and compare different approaches towards learning and encoding movements us- ing dynamical systems that have been developed by the AMARSi partners (in the past during the first 6 months of the project), and (2) to analyze their suitability to be used as adaptive modules, i.e. as building blocks for the complete architecture that will be devel- oped in the project. The document presents a total of eight approaches, in two groups: modules for discrete movements (i.e. with a clear goal where the movement stops) and for rhythmic movements (i.e. which exhibit periodicity). The basic formulation of each approach is presented together with some illustrative simulation results. Key character- istics such as the type of dynamical behavior, learning algorithm, generalization properties, stability analysis are then discussed for each approach. We then make a comparative analysis of the different approaches by comparing these characteristics and discussing their suitability for the AMARSi project

Real-time motor rotation frequency detection with event-based visual and spike-based auditory AER sensory integration for FPGA

Multisensory integration is commonly used in various robotic areas to collect more environmental information using different and complementary types of sensors. Neuromorphic engineers mimics biological systems behavior to improve systems performance in solving engineering problems with low power consumption. This work presents a neuromorphic sensory integration scenario for measuring the rotation frequency of a motor using an AER DVS128 retina chip (Dynamic Vision Sensor) and a stereo auditory system on a FPGA completely event-based. Both of them transmit information with Address-Event-Representation (AER). This integration system uses a new AER monitor hardware interface, based on a Spartan-6 FPGA that allows two operational modes: real-time (up to 5 Mevps through USB2.0) and data logger mode (up to 20Mevps for 33.5Mev stored in onboard DDR RAM). The sensory integration allows reducing prediction error of the rotation speed of the motor since audio processing offers a concrete range of rpm, while DVS can be much more accurate.Ministerio de Economía y Competitividad TEC2012-37868-C04-02/0

X-ray analog pixel array detector for single synchrotron bunch time-resolved imaging

Dynamic x-ray studies may reach temporal resolutions limited by only the x-ray pulse duration if the detector is fast enough to segregate synchrotron pulses. An analog integrating pixel array detector with in-pixel storage and temporal resolution of around 150 ns, sufficient to isolate pulses, is presented. Analog integration minimizes count-rate limitations and in-pixel storage captures successive pulses. Fundamental tests of noise and linearity as well as high-speed laser measurements are shown. The detector resolved individual bunch trains at the Cornell High Energy Synchrotron Source (CHESS) at levels of up to 3.7x10^3 x-rays/pixel/train. When applied to turn-by-turn x-ray beam characterization single-shot intensity measurements were made with a repeatability of 0.4% and horizontal oscillations of the positron cloud were detected. This device is appropriate for time-resolved Bragg spot single crystal experiments.Comment: 9 pages, 11 figure

Fast And Accurate Receiver Jitter Tolerance Extrapolation Using The Q-Factor Linear Fitting Method

A performance bit rates of more than 6 Gb/s is deemed as a common standard in high-speed interconnect system in conjunction with the recent enhancement of high-speed serial interface (HSSI). In industry, receiver (Rx) jitter tolerance (JTOL) measurement required to characterize the high-speed interconnect. Time required for conventional methods to complete Rx JTOL measurement for low bit error rate (BER) values normally took a week’s time depending on the data rate. In addition, a large number of bits is required to be transmitted hence resulting measurement cost as inefficient. This research project implements a method known as Q-factor linear fitting method to reduce the measurement time of the Rx JTOL at low BER by using high BER data. The result shows that the measurement of Rx JTOL using Q-factor linear fitting method using BER 10-10 data achieved 11x speed-up in comparison to direct measurement of Rx JTOL. The proposed methods of combined different level of BER values and increase more data points of higher BER able to significantly improve the accuracy of the Rx JTOL measurement result. The proposed method is successfully established in the experiment where the results obtained indicated relative error of Rx JTOL using Q-factor linear fitting method of BER 10-10 data are reduced from 9.47% to 3.31% after combining with the BER 10-11 data and relative error for Rx JTOL extrapolation measurement using BER 10-10 data at low temperature (-25˚C) is reduced from 9.47% to 5.43% by increasing the measurement data point from 20 data points to 30 data point