Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

Analog baseband circuits for WCDMA direct-conversion receivers

This thesis describes the design and implementation of analog baseband circuits for low-power single-chip WCDMA direct-conversion receivers. The reference radio system throughout the thesis is UTRA/FDD. The analog baseband circuit consists of two similar channels, which contain analog channel-select filters, programmable-gain amplifiers, and circuits that remove DC offsets. The direct-conversion architecture is described and the UTRA/FDD system characteristics are summarized. The UTRA/FDD specifications define the performance requirement for the whole receiver. Therefore, the specifications for the analog baseband circuit are obtained from the receiver requirements through calculations performed by hand. When the power dissipation of an UTRA/FDD direct-conversion receiver is minimized, the design parameters of an all-pole analog channel-select filter and the following Nyquist rate analog-to-digital converter must be considered simultaneously. In this thesis, it is shown that minimum power consumption is achieved with a fifth-order lowpass filter and a 15.36-MS/s Nyquist rate converter that has a 7- or 8-bit resolution. A fifth-order Chebyshev prototype with a passband ripple of 0.01 dB and a −3-dB frequency of 1.92-MHz is adopted in this thesis. The error-vector-magnitude can be significantly reduced by using a first-order 1.4-MHz allpass filter. The selected filter prototype fulfills all selectivity requirements in the analog domain. In this thesis, all the filter implementations use the opamp-RC technique to achieve insensitivity to parasitic capacitances and a high dynamic range. The adopted technique is analyzed in detail. The effect of the finite opamp unity-gain bandwidth on the filter frequency response can be compensated for by using passive methods. Compensation schemes that also track the process and temperature variations have been developed. The opamp-RC technique enables the implementation of low-voltage filters. The design and simulation results of a 1.5-V 2-MHz lowpass filter are discussed. The developed biasing scheme does not use any additional current to achieve the low-voltage operation, unlike the filter topology published previously elsewhere. Methods for removing DC offsets in UTRA/FDD direct-conversion receivers are presented. The minimum areas for cascaded AC couplings and DC-feedback loops are calculated. The distortion of the frequency response of a lowpass filter caused by a DC-feedback loop connected over the filter is calculated and a method for compensating for the distortion is developed. The time constant of an AC coupling can be increased using time-constant multipliers. This enables the implementation of AC couplings with a small silicon area. Novel time-constant multipliers suitable for systems that have a continuous reception, such as UTRA/FDD, are presented. The proposed time-constant multipliers only require one additional amplifier. In an UTRA/FDD direct-conversion receiver, the reception is continuous. In a low-power receiver, the programmable baseband gain must be changed during reception. This may produce large, slowly decaying transients that degrade the receiver performance. The thesis shows that AC-coupling networks and DC-feedback loops can be used to implement programmable-gain amplifiers, which do not produce significant transients when the gain is altered. The principles of operation, the design, and the practical implementation issues of these amplifiers are discussed. New PGA topologies suitable for continuously receiving systems have been developed. The behavior of these circuits in the presence of strong out-of-channel signals is analyzed. The interface between the downconversion mixers and the analog baseband circuit is discussed. The effect of the interface on the receiver noise figure and the trimming of mixer IIP2 are analyzed. The design and implementation of analog baseband circuits and channel-select filters for UTRA/FDD direct-conversion receivers are discussed in five application cases. The first case presents the analog baseband circuit for a chip-set receiver. A channel-select filter that has an improved dynamic range with a smaller supply current is presented next. The third and fifth application cases describe embedded analog baseband circuits for single-chip receivers. In the fifth case, the dual-mode analog baseband circuit of a quad-mode receiver designed for GSM900, DCS1800, PCS1900, and UTRA/FDD cellular systems is described. A new, highly linear low-power transconductor is presented in the fourth application case. The fourth application case also describes a channel-select filter. The filter achieves +99-dBV out-of-channel IIP2, +45-dBV out-of-channel IIP3 and 23-μVRMS input-referred noise with 2.6-mA current from a 2.7-V supply. In the fifth application case, a corresponding performance is achieved in UTRA/FDD mode. The out-of-channel IIP2 values of approximately +100 dBV achieved in this work are the best reported so far. This is also the case with the figure of merits for the analog channel-select filter and analog baseband circuit described in the fourth and fifth application cases, respectively. For equal power dissipation, bandwidth, and filter order, these circuits achieve approximately 10 dB and 15 dB higher spurious-free dynamic ranges, respectively, when compared to implementations that are published elsewhere and have the second best figure of merits.reviewe

Low-Noise Micro-Power Amplifiers for Biosignal Acquisition

There are many different types of biopotential signals, such as action potentials (APs), local field potentials (LFPs), electromyography (EMG), electrocardiogram (ECG), electroencephalogram (EEG), etc. Nerve action potentials play an important role for the analysis of human cognition, such as perception, memory, language, emotions, and motor control. EMGs provide vital information about the patients which allow clinicians to diagnose and treat many neuromuscular diseases, which could result in muscle paralysis, motor problems, etc. EEGs is critical in diagnosing epilepsy, sleep disorders, as well as brain tumors. Biopotential signals are very weak, which requires the biopotential amplifier to exhibit low input-referred noise. For example, EEGs have amplitudes from 1 μV [microvolt] to 100 μV [microvolt] with much of the energy in the sub-Hz [hertz] to 100 Hz [hertz] band. APs have amplitudes up to 500 μV [microvolt] with much of the energy in the 100 Hz [hertz] to 7 kHz [hertz] band. In wearable/implantable systems, the low-power operation of the biopotential amplifier is critical to avoid thermal damage to surrounding tissues, preserve long battery life, and enable wirelessly-delivered or harvested energy supply. For an ideal thermal-noise-limited amplifier, the amplifier power is inversely proportional to the input-referred noise of the amplifier. Therefore, there is a noise-power trade-off which must be well-balanced by the designers. In this work I propose novel amplifier topologies, which are able to significantly improve the noise-power efficiency by increasing the effective transconductance at a given current. In order to reject the DC offsets generated at the tissue-electrode interface, energy-efficient techniques are employed to create a low-frequency high-pass cutoff. The noise contribution of the high-pass cutoff circuitry is minimized by using power-efficient configurations, and optimizing the biasing and dimension of the devices. Sufficient common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are achieved to suppress common-mode interferences and power supply noises. Our design are fabricated in standard CMOS processes. The amplifiers’ performance are measured on the bench, and also demonstrated with biopotential recordings

Parkes-CDSCC telemetry array: Equipment design

A unique combination of Deep Space Network (DSN) and non-DSN facilities in Australia provided enhanced data return from the Voyager spacecraft as it encountered the planet Uranus. Many of the key elements are duplicated from Voyager's encounters with Jupiter and Saturn. Some are unique extensions of that technology

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Vibration control of ultra-high precision magnetic leadscrew using recurrent neural network

Ultra-high precision positioning is of strategic importance to modern industrial processes such as semiconductor manufacturing. Traditional drives with mechanical transmission elements exhibit nonlinearities such as friction, backlash and hysteresis which limit the system performance significantly. The magnetic leadscrew in this work belongs to the class of contactless drives which overcome the above mentioned limitations of contact-type drives. The operation is based on leadscrew/nut coupling but unlike mechanical Ieadscrews, the threads of the nut and the leadscrew are aligned magnetically and do not come in contact. Thus, hard nonlinearities are substantially reduced resulting in high precision and high resolution. The dynamics of the system are, however, lightly damped and result in vibration of the nut upto tens of microns peak-to-peak. Due to the high frequency of the modes, typically a few hundred Hz, the dynamics are difficult to control using conventional techniques, limited actuator bandwidth being one of the reasons. Active control must therefore be employed. This work develops a passband control scheme based on the Hilbert Transform which gives the orthogonal components of the oscillating modes. The components are extracted using a neural network to enhance the robustness of the controller. Performance of the controller is evaluated under self-resonance, forced oscillation and transient response. Self-resonance is shown to be completely eliminated while for forced oscillation, the axial gain is shown to be reduced. Stabilization time of the transient response is also significantly reduced, thereby confirming the vibration suppression capabilities of the controller

Efficient delta-sigma ADC for mobile audio applications based on a LabVIEW assisted architectural design flow

Questo lavoro di tesi è il risultato della fruttuosa collaborazione tra l’azienda multinazionale ST-Ericsson e il Dipartimento di Ingegneria dell’Informazione dell’Università di Pisa. ST-Ericsson è una delle aziende ”leader” nei mercati dei “modem“ e dei processori in banda base. Il gruppo di “mixed signal design“ nell’area di Zurigo (Svizzera) unitamente al gruppo basato a Bangalore (India) hanno, tra gli altri obbiettivi, la continua ricerca di soluzioni per migliorare l’efficienza ed il costo dei sotto-sistemi audio. Questa è stata quindi la base di lavoro per l’inizio di una collaborazione con l’accademia su tali temi. Lo studio è iniziato con una valutazione dello stato dell’arte dei “computer aided design tool” (CAD tool) per gli studi architetturali e per la validazione dei progetti dei convertitori delta-sigma sia in banda audio sia per applicazioni a larga ampiezza di banda, riscontrando una mancanza di flessibilità nell’area dei flussi per la scelta di architetture orientate al progetto. Sulla base di tali evidenze è stato sviluppato un nuovo “software” implementato in LabVIEW e finalizzato a guidare la scelta dei parametri di progetto di un convertitore analogico-digitale (ADC) delta-sigma. Tale “CAD tool” considera la minimizzazione dell’area di silicio già nella scelta dell’architettura lasciando al progettista la possibilità di implementare dei requisiti addizionali per la minimizzazione dell’area piuttosto che scegliere i parametri di progetto (coefficienti della risposta in frequenza) con il solo fine di ottenere le prestazioni desiderate. L’architettura della catena di “uplink” del processore in banda base è stata inoltre riprogettata e la funzionalità di alcuni blocchi è stata implementata nel ADC. Il controllo del guadagno, tradizionalmente effettuato da un amplificatore a guadagno variabile o “programmable gain amplifier” (PGA) attivato in corrispondenza degli attraversamenti dello zero rilevati da un “zero crossing detector” (ZCD), è stato inserito nell’anello di reazione del ADC attraverso un banco di condensatori selezionabili tramite controllo digitale. Gli effetti della commutazione del guadagno sul “dithering” e sulla traslazione del “idle-tone” sono state esaminati e sono state proposte delle soluzioni. Questo ha aperto alla possibilità di migliorare la qualità delle transizioni di guadagno attraverso un controllo a modulazione di larghezza dell’impulso o “Pulse Width Modulation” (PWM) che consente una variazione del guadagno e di conseguenza del segnale audio, molto più graduale rispetto a quanto avviene nelle soluzioni attualmente disponibili sul mercato. Infine un ADC in banda audio con area pari a 0.073 mm2 e consumo di corrente pari a 950 A da una tensione di alimentazione di 2.3 V, è stato realizzato in tecnologia CMOS 40nm. Il progetto è stato validato tramite la caratterizzazione sperimentale sia su un microchip di silicio a se’ stante contenente il solo ADC, sia sulla catena audio del processore in banda base G4860 che sta per essere adottato da Samsung per una prossima generazione di telefoni cellulari. Tra i principali obiettivi innovativi raggiunti si hanno: (i) Riduzione del 15% dell’area occupata dai condensatori commutati rispetto alle soluzioni di ADC riportati in letteratura con simili prestazioni, (ii) riduzione del 25% in area e del 30% in corrente nella catena di “uplink” audio sviluppata per un progetto GSM commerciale per mezzo dell’eliminazione sia del PGA che dello ZCD nel “front-end” audio, (iii) maggiore gradualità nel cambiamento del guadagno rispetto i dispositivi esistenti grazie ad una tecnica di controllo originale che è stata proposta per l’ottenimento di un brevetto da parte di ST-Ericsson

Low-noise amplifiers for integrated multi-mode direct-conversion receivers

The evolution of wireless telecommunication systems during the last decade has been rapid. During this time the design driver has shifted towards fast data applications instead of speech. In addition, the different systems may have a limited coverage, for example, limited to urban areas only. Thus, it has become important for a mobile terminal to be able to use different wireless systems, depending on the application chosen and the location of the terminal. The choice of receiver architecture affects the performance, size, and cost of the receiver. The superheterodyne receiver has hitherto been the dominant radio architecture, because of its good sensitivity and selectivity. However, superheterodyne receivers require expensive filters, which, with the existing technologies, cannot be integrated on the same chip as the receiver. Therefore, architectures using a minimum number of external components, such as direct conversion, have become popular. In addition, compared to the superheterodyne architecture, the direct-conversion architecture has benefits when multi-mode receivers, which are described in this thesis, are being designed. In this thesis, the limitations placed on the analog receiver by different system specifications are introduced. The estimations for the LNA specifications are derived from these specifications. In addition, the limitations imposed by different types of receiver architectures are described. The inductively-degenerated LNA is the basis for all the experimental circuits. The different components for this configuration are analyzed and compared to other commonly-used configurations in order to justify the use of an inductively-degenerated LNA. Furthermore, the design issues concerning the LNA-mixer interface in direct-conversion receivers are analyzed. Without knowing these limitations, it becomes difficult to understand the choices made in the experimental circuits. One of the key parts of this thesis describes the design and implementation of a single-chip multi-mode LNA, which is one of the key blocks in multi-mode receivers. The multi-mode structures in this thesis were developed for a direct-conversion receiver where only one system is activated at a time. The LNA interfaces to a pre-select filter and mixers and the different LNA components are analyzed in detail. Furthermore, the design issues related to possible interference from additional systems on single-chip receivers are analyzed and demonstrated. A typical receiver includes variable gain, which can be implemented both in the analog baseband and/or in the RF. If the variable gain is implemented in the RF parts, it is typically placed in the LNA or in a separate gain control stage. Several methods that can be used to implement a variable gain in the LNA are introduced and compared to each other. Furthermore, several of these methods are included in the experimental circuits. The last part of this thesis concentrates on four experimental circuits, which are described in this thesis. The first two chips describe an RF front-end and a direct-conversion receiver for WCDMA applications. The whole receiver demonstrates that it is possible to implement A/D converters on the same chip as sensitive RF blocks without significantly degrading receiver performance. The other two chips describe an RF front-end for WCDMA and GSM900 applications and a direct-conversion receiver for GSM900, DCS1800, PCS1900 and WCDMA systems. These ICs demonstrate the usability of the circuit structure developed and presented in this thesis. The chip area in the last multi-mode receiver is not significantly increased compared to corresponding single-system receivers.reviewe

Electrical Impedance Tomography for Biomedical Applications: Circuits and Systems Review

There has been considerable interest in electrical impedance tomography (EIT) to provide low-cost, radiation-free, real-time and wearable means for physiological status monitoring. To be competitive with other well-established imaging modalities, it is important to understand the requirements of the specific application and determine a suitable system design. This paper presents an overview of EIT circuits and systems including architectures, current drivers, analog front-end and demodulation circuits, with emphasis on integrated circuit implementations. Commonly used circuit topologies are detailed, and tradeoffs are discussed to aid in choosing an appropriate design based on the application and system priorities. The paper also describes a number of integrated EIT systems for biomedical applications, as well as discussing current challenges and possible future directions