Theoretical and Experimental Studies of Schottky Diodes That Use Aligned Arrays of Single Walled Carbon Nanotubes

We present theoretical and experimental studies of Schottky diodes that use aligned arrays of single walled carbon nanotubes. A simple physical model, taking into account the basic physics of current rectification, can adequately describe the single-tube and array devices. We show that for as grown array diodes, the rectification ratio, defined by the maximum-to-minimum-current-ratio, is low due to the presence of m-SWNT shunts. These tubes can be eliminated in a single voltage sweep resulting in a high rectification array device. Further analysis also shows that the channel resistance, and not the intrinsic nanotube diode properties, limits the rectification in devices with channel length up to ten micrometer.Comment: Nano Research, 2010, accepte

High-Yield of Memory Elements from Carbon Nanotube Field-Effect Transistors with Atomic Layer Deposited Gate Dielectric

Carbon nanotube field-effect transistors (CNT FETs) have been proposed as possible building blocks for future nano-electronics. But a challenge with CNT FETs is that they appear to randomly display varying amounts of hysteresis in their transfer characteristics. The hysteresis is often attributed to charge trapping in the dielectric layer between the nanotube and the gate. This study includes 94 CNT FET samples, providing an unprecedented basis for statistics on the hysteresis seen in five different CNT-gate configurations. We find that the memory effect can be controlled by carefully designing the gate dielectric in nm-thin layers. By using atomic layer depositions (ALD) of HfO$_{2}$ and TiO$_{2}$ in a triple-layer configuration, we achieve the first CNT FETs with consistent and narrowly distributed memory effects in their transfer characteristics.Comment: 6 pages, 3 figures; added one reference, text reformatted with smaller addition

Field-effect transistors assembled from functionalized carbon nanotubes

We have fabricated field effect transistors from carbon nanotubes using a novel selective placement scheme. We use carbon nanotubes that are covalently bound to molecules containing hydroxamic acid functionality. The functionalized nanotubes bind strongly to basic metal oxide surfaces, but not to silicon dioxide. Upon annealing, the functionalization is removed, restoring the electronic properties of the nanotubes. The devices we have fabricated show excellent electrical characteristics.Comment: 5 pages, 6 figure

Scalability of carbon-nanotube-based thin film transistors for flexible electronic devices manufactured using an all roll-to-roll gravure printing system.

To demonstrate that roll-to-roll (R2R) gravure printing is a suitable advanced manufacturing method for flexible thin film transistor (TFT)-based electronic circuits, three different nanomaterial-based inks (silver nanoparticles, BaTiO3 nanoparticles and single-walled carbon nanotubes (SWNTs)) were selected and optimized to enable the realization of fully printed SWNT-based TFTs (SWNT-TFTs) on 150-m-long rolls of 0.25-m-wide poly(ethylene terephthalate) (PET). SWNT-TFTs with 5 different channel lengths, namely, 30, 80, 130, 180, and 230 μm, were fabricated using a printing speed of 8 m/min. These SWNT-TFTs were characterized, and the obtained electrical parameters were related to major mechanical factors such as web tension, registration accuracy, impression roll pressure and printing speed to determine whether these mechanical factors were the sources of the observed device-to-device variations. By utilizing the electrical parameters from the SWNT-TFTs, a Monte Carlo simulation for a 1-bit adder circuit, as a reference, was conducted to demonstrate that functional circuits with reasonable complexity can indeed be manufactured using R2R gravure printing. The simulation results suggest that circuits with complexity, similar to the full adder circuit, can be printed with a 76% circuit yield if threshold voltage (Vth) variations of less than 30% can be maintained

Electronic Devices Based on Purified Carbon Nanotubes Grown By High Pressure Decomposition of Carbon Monoxide

The excellent properties of transistors, wires, and sensors made from single-walled carbon nanotubes (SWNTs) make them promising candidates for use in advanced nanoelectronic systems. Gas-phase growth procedures such as the high pressure decomposition of carbon monoxide (HiPCO) method yield large quantities of small diameter semiconducting SWNTs, which are ideal for use in nanoelectronic circuits. As-grown HiPCO material, however, commonly contains a large fraction of carbonaceous impurities that degrade properties of SWNT devices. Here we demonstrate a purification, deposition, and fabrication process that yields devices consisting of metallic and semiconducting nanotubes with electronic characteristics vastly superior to those of circuits made from raw HiPCO. Source-drain current measurements on the circuits as a function of temperature and backgate voltage are used to quantify the energy gap of semiconducting nanotubes in a field effect transistor geometry. This work demonstrates significant progress towards the goal of producing complex integrated circuits from bulk-grown SWNT material.Comment: 6 pages, 4 figures, to appear in Nature Material

High-Performance Carbon Nanotube Field-Effect Transistor with Tunable Polarities

State-of-the-art carbon nanotube field-effect transistors (CNFETs) behave as Schottky barrier (SB)-modulated transistors. It is known that vertical scaling of the gate oxide significantly improves the performance of these devices. However, decreasing the oxide thickness also results in pronounced ambipolar transistor characteristics and increased drain leakage currents. Using a novel device concept, we have fabricated high-performance, enhancement-mode CNFETs exhibiting n or p-type unipolar behavior, tunable by electrostatic and/or chemical doping, with excellent OFF-state performance and a steep subthreshold swing (S =63 mV/dec). The device design allows for aggressive oxide thickness and gate length scaling while maintaining the desired device characteristics.Comment: 26 pages, 12 figures, accepted for IEEE Trans. Nanotechnolog

A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design