A survey of behavioral-level partitioning systems

Many approaches have been developed to partition a system's behavioral description before a structural implementation is synthesized. We highlight the foundations and motivations for behavioral partitioning. We survey behavioral partitioning approaches, discussing abstraction levels, goals, major steps, and key assumptions in each

A 12-b 50Msample/s Pipeline Analog to Digital Converter

This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage structure. Correction of the pipeline is accomplished by measuring the offset and gain of each of the first six stages using subsequent stages. The measured values are used to calculate digtal values the compensate for the inaccuracies of the analog pipeline. Corrected digital values for each stage are stored in the pipeline and used to create corrected output codes. Errors caused by measuring the first six stages using uncalibrated stages are minimized by using extra switching circuitry during calibration

Design and prototype of an all digital system for baseband FM multiplex signal demodulation

textThe continuing increase in transistor densities and operation frequencies of digital circuits is leading to the replacement of many analog circuits by their digital circuit counterparts. This trend can be attributed to the flexibility and robustness provided by digital circuits over analog circuits. One application in which digital circuits are replacing analog circuits is in the modulation and demodulation of baseband frequency modulated (FM) radio signals. In this project, an all digital system for demodulating baseband FM Multiplex (MPX) signals is simulated, designed, and prototyped on a Xilinx Spartan-3AN FPGA. The design architecture is simulated using Scilab numerical computation software; implemented in Verilog Hardware Description Language; and tested using the digital to analog converters (DACs) on the Xilinx Spartan-3AN Starter Kit. The oscilloscope images at the end of this report show that the implemented system can successfully demodulate the 19kHz pilot tone, left channel signal, and right channel signal of a digitized FM MPX modulated signal sampled at 192kHz.Electrical and Computer Engineerin

Advances in Stereo Vision

Stereopsis is a vision process whose geometrical foundation has been known for a long time, ever since the experiments by Wheatstone, in the 19th century. Nevertheless, its inner workings in biological organisms, as well as its emulation by computer systems, have proven elusive, and stereo vision remains a very active and challenging area of research nowadays. In this volume we have attempted to present a limited but relevant sample of the work being carried out in stereo vision, covering significant aspects both from the applied and from the theoretical standpoints

Evaluation of the HARDMAN comparability methodology for manpower, personnel and training

The methodology evaluation and recommendation are part of an effort to improve Hardware versus Manpower (HARDMAN) methodology for projecting manpower, personnel, and training (MPT) to support new acquisition. Several different validity tests are employed to evaluate the methodology. The methodology conforms fairly well with both the MPT user needs and other accepted manpower modeling techniques. Audits of three completed HARDMAN applications reveal only a small number of potential problem areas compared to the total number of issues investigated. The reliability study results conform well with the problem areas uncovered through the audits. The results of the accuracy studies suggest that the manpower life-cycle cost component is only marginally sensitive to changes in other related cost variables. Even with some minor problems, the methodology seem sound and has good near term utility to the Army. Recommendations are provided to firm up the problem areas revealed through the evaluation

Design and Implementation of an Universal Lattice Decoder on FPGA

In wireless communication, MIMO (multiple input multiple output) is one of the promising technologies which improves the range and performance of transmission without increasing the bandwidth, while providing high rates. High speed hardware MIMO decoders are one of the keys to apply this technology in applications. In order to support the high data rates, the underlying hardware must have significant processing capabilities. FPGA improves the speed of signal processing using parallelism and reconfigurability advantages. The objective of this thesis is to develop an efficient hardware architectural model for the universal lattice decoder and prototype it on FPGA. The original algorithm is modified to ensure the high data rate via taking the advantage of FPGA features. The simulation results of software, hardware are verified and the BER performance of both the algorithms is estimated. The system prototype of the decoder with 4-transmit and 4-receive antennas using a 4-PAM (Pulse amplitude modulation) supports 6.32 Mbit/s data rate for parallelpipeline implementation on FPGA platform, which is about two orders of magnitude faster than its DSP implementation

FPGA Hardware Accelerators - Case Study on Design Methodologies and Trade-Offs

Previous research has shown that the performance of any computation is directly related to the architecture on which it is performed. As a result, the performance of compute intensive applications can be improved using heterogeneous systems. These systems consist of various processor architectures such as CPU, FPGA, DSP, and GPU. Individual computations can be performed in parallel on different processor architecrues within the heterogeneous system. Computations are performed by utilizing existing designs from implementation libraries. There is a lack of FPGA accelerators for use in these libraries and as such additional implementations need to be designed. Different design methodologies for developing FPGA accelerators result in implementations that vary in performance, design time, and resource utilization. A particular method and supporting toolset may produce better results for one type of design than another. The customary method for designing FPGA accelerators is to develop the system architecture from an algorithm and model it using a hardware decription language (HDL). Another method is to convert directly from a software implementation to HDL. This process is known as high level synthesis (HLS). The advantages and disadvantages of these two techniques can be examined through comparison of different linear algebra operations. Many linear algebra operations are parallel in nature which makes them potentially good choices to speedup through implementation on an FPGA. In particular, matrix multiplication is an excellent candidate for examination due to not only its parallelism but also its multitude of different algorithms. The goal of this research is to design different matrix multiplication accelerators and provide insight into the advantages and disadvantages of each design procedure

Multiple voltage scheme with frequency variation for power minimization of pipelined circuits at high-level synthesis

High-Level Synthesis (HLS) is defined as a translation process from a behavioral description into structural description. The high-level synthesis process consists of three interdependent phases: scheduling, allocation and binDing The order of the three phases varies depending on the design flow. There are three important quality measures used to support design decision, namely size, performance and power consumption. Recently, with the increase in portability, the power consumption has become a very dominant factor in the design of circuits. The aim of low-power high-level synthesis is to schedule operations to minimize switching activity and select low power modules while satisfying timing constraints. This thesis presents a heuristic that helps minimize power consumption by operating the functional units at multiple voltages and varied clock frequencies. The algorithm presented here deals with pipelined operations where multiple instance of the same operation are carried out. The algorithm was implemented using C++, on LINUX platform

A Pipeline Analog-To-Digital Converter for a Plasma Impedance Probe

Space instrumentation technology is an essential tool for rocket and satellite research, and is expected to become popular in commercial and military operations in fields such as radar, imaging, and communications. These instruments are traditionally implemented on printed circuit boards using discrete general-purpose Analog-to-Digital Converter (ADC) devices and other components. A large circuit board is not convenient for use in micro-satellite deployments, where the total payload volume is limited to roughly one cubic foot. Because micro-satellites represent a fast growing trend in satellite research and development, there is motivation to explore miniaturized custom application-specific integrated circuit (ASIC) designs to reduce the volume and power consumption occupied by instrument electronics. In this thesis, a model of a new Plasma Impedance Probe (PIP) architecture, which utilizes a custom-built ADC along with other analog and digital components, is proposed. The model can be fully integrated to produce a low-power, miniaturized impedance probe