A parallel Viterbi decoder for block cyclic and convolution codes

We present a parallel version of Viterbi's decoding procedure, for which we are able to demonstrate that the resultant task graph has restricted complexity in that the number of communications to or from any processor cannot exceed 4 for BCH codes. The resulting algorithm works in lock step making it suitable for implementation on a systolic processor array, which we have implemented on a field programmable gate array and demonstrate the perfect scaling of the algorithm for two exemplar BCH codes. The parallelisation strategy is applicable to all cyclic codes and convolution codes. We also present a novel method for generating the state transition diagrams for these codes

An Iteratively Decodable Tensor Product Code with Application to Data Storage

The error pattern correcting code (EPCC) can be constructed to provide a syndrome decoding table targeting the dominant error events of an inter-symbol interference channel at the output of the Viterbi detector. For the size of the syndrome table to be manageable and the list of possible error events to be reasonable in size, the codeword length of EPCC needs to be short enough. However, the rate of such a short length code will be too low for hard drive applications. To accommodate the required large redundancy, it is possible to record only a highly compressed function of the parity bits of EPCC's tensor product with a symbol correcting code. In this paper, we show that the proposed tensor error-pattern correcting code (T-EPCC) is linear time encodable and also devise a low-complexity soft iterative decoding algorithm for EPCC's tensor product with q-ary LDPC (T-EPCC-qLDPC). Simulation results show that T-EPCC-qLDPC achieves almost similar performance to single-level qLDPC with a 1/2 KB sector at 50% reduction in decoding complexity. Moreover, 1 KB T-EPCC-qLDPC surpasses the performance of 1/2 KB single-level qLDPC at the same decoder complexity.Comment: Hakim Alhussien, Jaekyun Moon, "An Iteratively Decodable Tensor Product Code with Application to Data Storage

Development of Simulation Components for Wireless Communication

abstract: This thesis work present the simulation of Bluetooth and Wi-Fi radios in real life interference environments. When information is transmitted via communication channels, data may get corrupted due to noise and other channel discrepancies. In order to receive the information safely and correctly, error correction coding schemes are generally employed during the design of communication systems. Usually the simulations of wireless communication systems are done in such a way that they focus on some aspect of communications and neglect the others. The simulators available currently will either do network layer simulations or physical layer level simulations. In many situations, simulations are required which show inter-layer aspects of communication systems. For all such scenarios, a simulation environment, WiscaComm which is based on time-domain samples is built. WiscaComm allows the study of network and physical layer interactions in detail. The advantage of time domain sampling is that it allows the simulation of different radios together which is better than the complex baseband representation of symbols. The environment also supports study of multiple protocols operating simultaneously, which is of increasing importance in today's environment.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Design a High Secure Adaptive VETERBI Encoder and Decoder Architectures

Mainly, Viterbi algorithm [V.A] is utilized in various applications such as cellular relay, satellite communication, and networks of wireless local area. This algorithm is mainly applied to the decoding conventional codes and also to automatic speech recognition and storage devices. In architecture of Viterbi algorithm, we are utilizing scheme of error detection which is based on the low complexity and low latency. The main benefit of this proposed system is that it gives reliable requirements and as well as performance degradation. We utilize three variants in the system which is recomputed with the encoded operands. Thus, this system is modified when we detect the both permanent faults [P.F] and transient faults which are mixed with signature based methods. Here, we are utilizing architecture of instrumented decoder for the motive of extensive error detection assessments. For the motive of bench mark we are improving the both application specific integrated circuit and field programmed gate array. Depend upon the reliability objectives and performance degradation tolerance, the proposed system is utilized

Iterative decoding for error resilient wireless data transmission

Both turbo codes and LDPC codes form two new classes of codes that offer energy efficiencies close to theoretical limit predicted by Claude Shannon. The features of turbo codes include parallel code catenation, recursive convolutional encoders, punctured convolutional codes and an associated decoding algorithm. The features of LDPC codes include code construction, encoding algorithm, and an associated decoding algorithm. This dissertation specifically describes the process of encoding and decoding for both turbo and LDPC codes and demonstrates the performance comparison between theses two codes in terms of some performance factors. In addition, a more general discussion of iterative decoding is presented. One significant contribution of this dissertation is a study of some major performance factors that intensely contribute in the performance of both turbo codes and LDPC codes. These include Bit Error Rate, latency, code rate and computational resources. Simulation results show the performance of turbo codes and LDPC codes under different performance factors

Polynomials in Error Detection and Correction in Data Communication System

The chapter gives an overview of the various types of errors encountered in a communication system. It discusses the various error detection and error correction codes. The role of polynomials in error detection and error correction is discussed in detail with the architecture for practical implementation of the codes in a communication channel

Studies in Error Correction Coding

For a proper understanding of the implementation of error correction coding schemes, a basic knowledge of communication channels and networks is necessary. Communication channels incur several types of errors, including noise and signal attenuation. Consequently, the benefits of a particular error control scheme are determined by the errors which occur most frequently. First, the types of transmissions across which errors occur will be considered. Subsequently, the types of errors that can appear during these transmissions and a short discussion of the cause of errors are necessary to understand the several types of errors that can occur. Afterward, the implementation of several major coding schemes will be discussed, including block codes, linear codes, and convolutional codes. Convolutional codes will specifically be discussed in terms of turbo codes and low-density parity check codes. Lastly, research of error correction coding schemes will involve several kinds of resources, including textbooks, journal articles, and technical publications. These resources will be used for the understanding of a practical implementation of an error correction coding scheme