Area-driven partial reconfiguration for SEU mitigation on SRAM-based FPGAs

This paper presents an area-driven Field-Programmable Gate Array (FPGA) scrubbing technique based on partial reconfiguration for Single Event Upset (SEU) mitigation. The proposed method is compared with existing techniques such as blind and on-demand scrubbing on a novel SEU mitigation framework implemented on the ZYNQ platform, supporting various SEU and scrubbing rates. A design space exploration on the availability versus data transfers from a Double Data Rate Type 3 (DDR3) memory, shows that our approach outperforms blind scrubbing for a range of availability values when a second order polynomial IP is targeted. A comparison to an existing on-demand scrubbing technique based on Dual Modular Redundancy (DMR) shows that our approach saves up to 46% area for the same case study

Enhancing Real-time Embedded Image Processing Robustness on Reconfigurable Devices for Critical Applications

Nowadays, image processing is increasingly used in several application fields, such as biomedical, aerospace, or automotive. Within these fields, image processing is used to serve both non-critical and critical tasks. As example, in automotive, cameras are becoming key sensors in increasing car safety, driving assistance and driving comfort. They have been employed for infotainment (non-critical), as well as for some driver assistance tasks (critical), such as Forward Collision Avoidance, Intelligent Speed Control, or Pedestrian Detection. The complexity of these algorithms brings a challenge in real-time image processing systems, requiring high computing capacity, usually not available in processors for embedded systems. Hardware acceleration is therefore crucial, and devices such as Field Programmable Gate Arrays (FPGAs) best fit the growing demand of computational capabilities. These devices can assist embedded processors by significantly speeding-up computationally intensive software algorithms. Moreover, critical applications introduce strict requirements not only from the real-time constraints, but also from the device reliability and algorithm robustness points of view. Technology scaling is highlighting reliability problems related to aging phenomena, and to the increasing sensitivity of digital devices to external radiation events that can cause transient or even permanent faults. These faults can lead to wrong information processed or, in the worst case, to a dangerous system failure. In this context, the reconfigurable nature of FPGA devices can be exploited to increase the system reliability and robustness by leveraging Dynamic Partial Reconfiguration features. The research work presented in this thesis focuses on the development of techniques for implementing efficient and robust real-time embedded image processing hardware accelerators and systems for mission-critical applications. Three main challenges have been faced and will be discussed, along with proposed solutions, throughout the thesis: (i) achieving real-time performances, (ii) enhancing algorithm robustness, and (iii) increasing overall system's dependability. In order to ensure real-time performances, efficient FPGA-based hardware accelerators implementing selected image processing algorithms have been developed. Functionalities offered by the target technology, and algorithm's characteristics have been constantly taken into account while designing such accelerators, in order to efficiently tailor algorithm's operations to available hardware resources. On the other hand, the key idea for increasing image processing algorithms' robustness is to introduce self-adaptivity features at algorithm level, in order to maintain constant, or improve, the quality of results for a wide range of input conditions, that are not always fully predictable at design-time (e.g., noise level variations). This has been accomplished by measuring at run-time some characteristics of the input images, and then tuning the algorithm parameters based on such estimations. Dynamic reconfiguration features of modern reconfigurable FPGA have been extensively exploited in order to integrate run-time adaptivity into the designed hardware accelerators. Tools and methodologies have been also developed in order to increase the overall system dependability during reconfiguration processes, thus providing safe run-time adaptation mechanisms. In addition, taking into account the target technology and the environments in which the developed hardware accelerators and systems may be employed, dependability issues have been analyzed, leading to the development of a platform for quickly assessing the reliability and characterizing the behavior of hardware accelerators implemented on reconfigurable FPGAs when they are affected by such faults

An Adaptive Modular Redundancy Technique to Self-regulate Availability, Area, and Energy Consumption in Mission-critical Applications

As reconfigurable devices\u27 capacities and the complexity of applications that use them increase, the need for self-reliance of deployed systems becomes increasingly prominent. A Sustainable Modular Adaptive Redundancy Technique (SMART) composed of a dual-layered organic system is proposed, analyzed, implemented, and experimentally evaluated. SMART relies upon a variety of self-regulating properties to control availability, energy consumption, and area used, in dynamically-changing environments that require high degree of adaptation. The hardware layer is implemented on a Xilinx Virtex-4 Field Programmable Gate Array (FPGA) to provide self-repair using a novel approach called a Reconfigurable Adaptive Redundancy System (RARS). The software layer supervises the organic activities within the FPGA and extends the self-healing capabilities through application-independent, intrinsic, evolutionary repair techniques to leverage the benefits of dynamic Partial Reconfiguration (PR). A SMART prototype is evaluated using a Sobel edge detection application. This prototype is shown to provide sustainability for stressful occurrences of transient and permanent fault injection procedures while still reducing energy consumption and area requirements. An Organic Genetic Algorithm (OGA) technique is shown capable of consistently repairing hard faults while maintaining correct edge detector outputs, by exploiting spatial redundancy in the reconfigurable hardware. A Monte Carlo driven Continuous Markov Time Chains (CTMC) simulation is conducted to compare SMART\u27s availability to industry-standard Triple Modular Technique (TMR) techniques. Based on nine use cases, parameterized with realistic fault and repair rates acquired from publically available sources, the results indicate that availability is significantly enhanced by the adoption of fast repair techniques targeting aging-related hard-faults. Under harsh environments, SMART is shown to improve system availability from 36.02% with lengthy repair techniques to 98.84% with fast ones. This value increases to five nines (99.9998%) under relatively more favorable conditions. Lastly, SMART is compared to twenty eight standard TMR benchmarks that are generated by the widely-accepted BL-TMR tools. Results show that in seven out of nine use cases, SMART is the recommended technique, with power savings ranging from 22% to 29%, and area savings ranging from 17% to 24%, while still maintaining the same level of availability

New Design Techniques for Dynamic Reconfigurable Architectures

L'abstract è presente nell'allegato / the abstract is in the attachmen

Fault Tolerant DC–DC Converters at Homes and Offices

The emergence of direct current (DC) microgrids within the context of residential buildings and offices brings in a whole new paradigm in energy distribution. As a result, a set of technical challenges arise, concerning the adoption of efficient, cost-effective, and reliable DC-compatible power conditioning solutions, suitable to interface DC microgrids and energy consuming elements. This thesis encompasses the development of DC–DC power conversion solutions, featuring improved availability and efficiency, suitable to meet the requirements of a comprehensive set of end-uses commonly found in homes and offices. Based on the energy consumption profiles and requirements of the typical elements found at homes and offices, three distinctive groups are established: light-emitting diode (LED) lighting, electric vehicle (EV) charging, and general appliances. For each group, a careful evaluation of the criteria to fulfil is performed, based on which at least one DC–DC power converter is selected and investigated. Totally, a set of five DC–DC converter topologies are addressed in this work, being specific aspects related to fault diagnosis and/or fault tolerance analysed with particular detail in two of them. Firstly, mathematical models are described for LED devices and EV batteries, for the development of a theoretical analysis of the systems’ operation through computational simulations. Based on a compilation of requirements to account for in each end-use (LED lighting, EV charging, and general appliances), brief design considerations are drawn for each converter topology, regarding their architecture and control strategy. Aiming a detailed understanding of the two DC–DC power conversion systems subjected to thorough evaluation in this work – interleaved boost converter and fault-tolerant single-inductor multiple-output (SIMO) converter – under both normal and abnormal conditions, the operation of the systems is evaluated in the presence of open-circuit (OC) faults. Parameters of interest are monitored and evaluated to understand how the failures impact the operation of the entire system. At this stage, valuable information is obtained for the development of fault diagnosis strategies. Taking profit of the data collected in the analysis, a novel fault diagnostic strategy is presented, targeting interleaved DC–DC boost converters for general appliances. Ease of implementation, fast diagnostic and robustness against false alarms distinguish the proposed approach over the state-of-the-art. Its effectiveness is confirmed through a set of operation scenarios, implemented in both simulation environment and experimental context. Finally, an extensive set of reconfiguration strategies is presented and evaluated, aiming to grant fault tolerance capability to the multiple DC–DC converter topologies under analysis. A hybrid reconfiguration approach is developed for the interleaved boost converter. It is demonstrated that the combination of reconfiguration strategies promotes remarkable improvements on the post-fault operation of the converter. In addition, an alternative SIMO converter architecture, featuring inherent tolerance against OC faults, is presented and described. To exploit the OC fault tolerance capability of the fault-tolerant SIMO converter, a converter topology targeted at residential LED lighting systems, two alternative reconfiguration strategies are presented and evaluated in detail. Results obtained from computational simulations and experimental tests confirm the effectiveness of the approaches. To further improve the fault-tolerant SIMO converter with regards to its robustness against sensor faults, while simplifying its hardware architecture, a sensorless current control strategy is presented. The proposed control strategy is evaluated resorting to computational simulations.O surgimento de micro-redes em corrente contínua (CC) em edifícios residenciais e de escritórios estabelece um novo paradigma no domínio da distribuição de energia. Como consequência disso, surge uma panóplia de desafios técnicos ligados à adopção de soluções de conversão de energia, compatíveis com CC, que demonstrem ser eficientes, rentáveis e fiáveis, capazes de estabelecer a interface entre micro-redes em CC e as cargas alimentadas por esse sistema de energia. Até aos dias de hoje, os conversores CC–CC têm vindo a ser maioritariamente utilizados em aplicações de nicho, que geralmente envolvem níveis de potência reduzidos. Porém, as perspectivas futuras apontam para a adopção, em larga escala, destas tecnologias de conversão de energia, também em equipamentos eléctricos residenciais e de escritórios. Tal como qualquer outra tecnologia de conversão electrónica de potência, os conversores CC–CC podem ver o seu funcionamento afectado por falhas que degradam o seu bom funcionamento, sendo que essas falhas acabam por afectar não apenas os conversores em si, mas também as cargas que alimentam, limitando assim o tempo de vida útil do conjunto conversor + carga. Desta forma, é fulcral localizar a origem da falha, para que possam ser adoptadas acções correctivas, capazes de limitar as consequências nefastas associadas à falha. Para responder a este desafio, esta tese contempla o desenvolvimento de soluções de conversão de energia CC–CC altamente eficientes e fiáveis, capazes de responder a requisitos impostos por um conjunto alargado de equipamentos frequentemente encontrados em habitações e escritórios. Com base nos perfis de consumo de energia eléctrica e nos requisitos impostos pelas cargas tipicamente utilizadas em habitações e escritórios, são estabelecidos três grupos distintos: iluminação através de díodos emissores de luz, carregamento de veículo eléctrico (VE) e aparelhos eléctricos em geral. Para cada grupo, é efectuada uma avaliação cuidadosa dos critérios a respeitar, sendo com base nesses critérios que será escolhida e investigada pelo menos uma topologia de conversor CC–CC. No total, são abordadas cinco topologias de conversores CC–CC distintas, sendo que os aspectos ligados ao diagnóstico de avarias e/ou tolerância a falhas são analisados com particular detalhe em duas dessas topologias. Inicialmente, são estabelecidos modelos matemáticos descritivos do comportamento das principais cargas consideradas no estudo – díodos emissores de luz e baterias de VEs – visando a análise teórica do funcionamento dos sistemas em estudo, suportada por simulações computacionais. Com base numa compilação de requisitos a ter em conta em cada aplicação – iluminação através de díodos emissores de luz, carregamento de veículo eléctrico (VE) e aparelhos eléctricos em geral – são estabelecidas considerações ligadas à escolha de cada topologia de conversor não isolado, no que respeita à sua arquitectura e estratégia de controlo. Visando o conhecimento aprofundado das duas topologias de conversor CC–CC alvo de particular enfoque neste trabalho – conversor entrelaçado elevador e conversor de entrada única e múltiplas saídas, tolerante a falhas – quer em funcionamento normal, quer em funcionamento em modo de falha, é avaliado o funcionamento de ambas as topologias na presença de falhas de circuito aberto nos semicondutores activos. Para o efeito, são monitorizados e analisados parâmetros úteis à percepção da forma como os modos de falha avaliados neste trabalho impactam o funcionamento de todo o sistema. Nesta fase, é obtida informação fundamental ao desenvolvimento de estratégias de diagnóstico de avarias, particularmente indicadas para avarias de circuito aberto nos semicondutores activos dos conversores em estudo. Com base na informação recolhida anteriormente, é apresentada uma nova estratégia de diagnóstico de avarias direccionada a conversores CC–CC elevadores entrelaçados utilizados em aparelhos eléctricos, em geral. Facilidade de implementação, rapidez e robustez contra falsos positivos são algumas das características que distinguem a estratégia proposta em relação ao estado da arte. A sua efectividade é confirmada com recurso a uma multiplicidade de cenários de funcionamento, implementados quer em ambiente de simulação, quer em contexto experimental. Por fim, é apresentada e avaliada uma gama alargada de estratégias de reconfiguração, que visam assegurar a tolerância a falhas das diversas topologias de conversores CC–CC em estudo. É desenvolvida uma estratégia de reconfiguração híbrida, direccionada ao conversor entrelaçado elevador, que combina múltiplas medidas de reconfiguração mais simples num único procedimento. Demonstra-se que a combinação de múltiplas estratégias de reconfiguração introduz melhorias substanciais no funcionamento do conversor ao longo do período pós-falha, ao mesmo tempo que assegura a manutenção da qualidade da energia à entrada e saída do conversor reconfigurado. Noutra frente, é apresentada e descrita uma arquitectura alternativa do conversor de entrada única e múltiplas saídas, com tolerância a falhas de circuito aberto. Através da configuração proposta, é possível manter o fornecimento de energia eléctrica a todas as saídas do conversor. Para tirar máximo proveito da tolerância a falhas do conversor de entrada única e múltiplas saídas, uma topologia de conversor indicada para sistemas residenciais de iluminação baseados em díodos emissores de luz, são apresentadas e avaliadas duas estratégias de reconfiguração do conversor, exclusivamente baseadas na adaptação do controlo aplicado ao conversor. Os resultados de simulação computacional e os resultados experimentais obtidos confirmam a efectividade das abordagens adoptadas, através da melhoria da qualidade da energia eléctrica fornecida às diversas saídas do conversor. São assim asseguradas condições essenciais ao funcionamento ininterrupto e estável dos sistemas de iluminação, já que a qualidade da energia eléctrica fornecida aos sistemas de iluminação tem impacto directo na qualidade da luz produzida. Por fim, e para aprimorar o conversor de entrada única e múltiplas saídas tolerante a falhas, no que respeita à sua robustez contra falhas em sensores, é apresentada uma estratégia de controlo de corrente que evita o recurso excessivo a sensores e, ao mesmo tempo, simplifica a estrutura de controlo do conversor. A estratégia apresentada é avaliada através de simulações computacionais. A abordagem apresentada assume vantagens em múltiplos domínios, sendo de destacar vantagens como a melhoria da fiabilidade de todo o sistema de iluminação (conversor + carga), os ganhos atingidos ao nível do rendimento, a redução do custo de implementação da solução, ou a simplificação da estrutura de controlo.This work was supported by the Portuguese Foundation for Science and Technology (FCT) under grant number SFRH/BD/131002/2017, co-funded by the Ministry of Science, Technology and Higher Education (MCTES), by the European Social Fund (FSE) through the ‘Programa Operacional Regional Centro’ (POR-Centro), and by the Human Capital Operational Programme (POCH)

Design techniques for xilinx virtex FPGA configuration memory scrubbers

SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers

Fault Tolerant Nanosatellite Computing on a Budget

In this contribution, we present a CubeSat-compatible on-board computer (OBC) architecture that offers strong fault tolerance to enable the use of such spacecraft in critical and long-term missions. We describe in detail the design of our OBC’s breadboard setup, and document its composition from the component-level, all the way down to the software level. Fault tolerance in this OBC is achieved without resorting to radiation hardening, just intelligent through software. The OBC ages graceful, and makes use of FPGA-reconfiguration and mixed criticality. It can dynamically adapt to changing performance requirements throughout a space mission. We developed a proof-of-concept with several Xilinx Ultrascale and Ultrascale+ FPGAs. With the smallest Kintex Ultrascale+ KU3P device, we achieve 1.94W total power consumption at 300Mhz, well within the power budget range of current 2U CubeSats. To our knowledge, this is the first scalable and COTS-based, widely reproducible OBC solution which can offer strong fault coverage even for small CubeSats. To reproduce this OBC architecture, no custom-written, proprietary, or protected IP is needed, and the needed design tools are available free-of-charge to academics. All COTS components required to construct this architecture can be purchased on the open market, and are affordable even for academic and scientific CubeSat developers

VR-ZYCAP: A versatile resourse-level ICAP controller for ZYNQ SOC

This article belongs to the Special Issue Architecture and CAD for Field-Programmable Gate Arrays (FPGAs)Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches.This research was funded by Spanish Ministry of Science and Innovation under the ACHILLES project, grant number PID2019-104207RB-I00 and by Taif University Researchers Supporting fund, grant number (TURSP-2020/144), Taif University, Taif, Saudi Arabia