Nonlinear switched-current CMOS IC for random signal generation

A nonlinear switched-current circuit is presented that implements a chaotic algorithm for the generation of broadband, white analogue noise. The circuit has been fabricated in a double-metal, single-poly 1.6µm CMOS technology and uses a novel, highly accurate CMOS circuit strategy to realise piecewise-linear characteristics in the current-mode domain. Measurements from the silicon prototype show a flat spectrum from DC to ~30% of the clock frequency, for a clock frequency of 500kHz

Implementation of a secure digital chaotic communication scheme on a DSP board

In this paper, a new a secure communication scheme using chaotic signal for transmitting binary digital signals is proposed and which is then implemented on a Digital Signal Processor (DSP) board. The method uses the idea of indirect coupled synchronization for generating the same keystream in the transmitter and receiver side. This chaotic keystream is applied to encrypt the message signal before being modulated with a chaotic carrier generated from the transmitter. Discrete chaotic maps, 3D Henon map and Lorenz system are used as transmitter/receiver and key generators respectively. The overall system is experimentally implemented in the TMS320C6713 DSK board using code composer and Simulink showing the successful message extraction thus proving the feasibility of the system in the DSP board

A pseudo-matched filter for chaos

A matched filter maximizes the signal-to-noise ratio of a signal. In the recent work of Corron et al. [Chaos 20, 023123 (2010)], a matched filter is derived for the chaotic waveforms produced by a piecewise-linear system. Motivated by these results, we describe a pseudo-matched filter, which removes noise from the same chaotic signal. It consists of a notch filter followed by a first-order, low-pass filter. We compare quantitatively the matched filter's performance to that of our pseudo-matched filter using correlation functions in a simulated radar application. On average, the pseudo-matched filter performs with a correlation signal-to-noise ratio that is 2.0 dB below that of the matched filter. Our pseudo-matched filter, though somewhat inferior in comparison to the matched filter, is easily realizable at high speed (> 1 GHz) for potential radar applications

Compressive Imaging Using RIP-Compliant CMOS Imager Architecture and Landweber Reconstruction

In this paper, we present a new image sensor architecture for fast and accurate compressive sensing (CS) of natural images. Measurement matrices usually employed in CS CMOS image sensors are recursive pseudo-random binary matrices. We have proved that the restricted isometry property of these matrices is limited by a low sparsity constant. The quality of these matrices is also affected by the non-idealities of pseudo-random number generators (PRNG). To overcome these limitations, we propose a hardware-friendly pseudo-random ternary measurement matrix generated on-chip by means of class III elementary cellular automata (ECA). These ECA present a chaotic behavior that emulates random CS measurement matrices better than other PRNG. We have combined this new architecture with a block-based CS smoothed-projected Landweber reconstruction algorithm. By means of single value decomposition, we have adapted this algorithm to perform fast and precise reconstruction while operating with binary and ternary matrices. Simulations are provided to qualify the approach.Ministerio de Economía y Competitividad TEC2015-66878-C3-1-RJunta de Andalucía TIC 2338-2013Office of Naval Research (USA) N000141410355European Union H2020 76586

Performance of direct-oversampling correlator-type receivers in chaos-based DS-CDMA systems over frequency non-selective fading channels

In this paper, we present a study on the performance of direct-oversampling correlator-type receivers in chaos-based direct-sequence code division multiple access systems over frequency non-selective fading channels. At the input, the received signal is sampled at a sampling rate higher than the chip rate. This oversampling step is used to precisely determine the delayed-signal components from multipath fading channels, which can be combined together by a correlator for the sake of increasing the SNR at its output. The main advantage of using direct-oversampling correlator-type receivers is not only their low energy consumption due to their simple structure, but also their ability to exploit the non-selective fading characteristic of multipath channels to improve the overall system performance in scenarios with limited data speeds and low energy requirements, such as low-rate wireless personal area networks. Mathematical models in discrete-time domain for the conventional transmitting side with multiple access operation, the generalized non-selective Rayleigh fading channel, and the proposed receiver are provided and described. A rough theoretical bit-error-rate (BER) expression is first derived by means of Gaussian approximation. We then define the main component in the expression and build its probability mass function through numerical computation. The final BER estimation is carried out by integrating the rough expression over possible discrete values of the PFM. In order to validate our findings, PC simulation is performed and simulated performance is compared with the corresponding estimated one. Obtained results show that the system performance get better with the increment of the number of paths in the channel.Peer ReviewedPostprint (author's final draft

Microcontroller-based random number generator implementation by using discrete chaotic maps

In recent decades, chaos theory has been used in different engineering applications of different disciplines. Discrete chaotic maps can be used in encryption applications for digital applications. In this study, firstly, Lozi, Tinkerbell and Barnsley Fern discrete chaotic maps are implemented based on microcontroller. Then, microcontroller based random number generator is implemented by using the three different two-dimensional discrete chaotic maps. The designed random number generator outputs are applied to NIST (National Institute of Standards and Technology) 800-22 and FIPS (Federal Information Processing Standard) tests for randomness validity. The random numbers are successful in all tests

Ultra-high-frequency piecewise-linear chaos using delayed feedback loops

We report on an ultra-high-frequency (> 1 GHz), piecewise-linear chaotic system designed from low-cost, commercially available electronic components. The system is composed of two electronic time-delayed feedback loops: A primary analog loop with a variable gain that produces multi-mode oscillations centered around 2 GHz and a secondary loop that switches the variable gain between two different values by means of a digital-like signal. We demonstrate experimentally and numerically that such an approach allows for the simultaneous generation of analog and digital chaos, where the digital chaos can be used to partition the system's attractor, forming the foundation for a symbolic dynamics with potential applications in noise-resilient communications and radar

A Novel TRNG Based on Traditional ADC Nonlinear Effect and Chaotic Map for IoT Security and Anticollision

In the rapidly developing Internet of Things (IoT) applications, how to achieve rapid identification of massive devices and secure the communication of wireless data based on low cost and low power consumption is the key problem to be solved urgently. This paper proposes a novel true random number generator (TRNG) based on ADC nonlinear effect and chaotic map, which can be implemented by traditional processors with built-in ADCs, such as MCU, DSP, ARM, and FPGA. The processor controls the ADC to sample the changing input signal to obtain the digital signal DADC and then extracts some bits of DADC to generate the true random number (TRN). At the same time, after a delay based on DADC, the next time ADC sampling is carried out, and the cycle continues until the processor stops generating the TRN. Due to the nonlinear effect of ADC, the DADC obtained from each sampling is stochastic, and the changing input signal will sharply change the delay time, thus changing the sampling interval (called random interval sampling). As the input signal changes, DADC with strong randomness is obtained. The whole operation of the TRNG resembles a chaotic map, and this method also eliminates the pseudorandom property of chaotic map by combining the variable input signal (including noise) with the nonlinear effect of ADC. The simulation and actual test data are verified by NIST, and the verification results show that the random numbers generated by the proposed method have strong randomness and can be used to implement TRNG. The proposed TRNG has the advantages of low cost, low power consumption, and strong compatibility, and the rate of generating true random number is more than 1.6 Mbps (determined by ADC sampling rate and processor frequency), which is very suitable for IoT sensor devices for security encryption algorithms and anticollision