Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

Romoth J, Porrmann M, Rückert U. Survey of FPGA applications in the period 2000 – 2015 (Technical Report).; 2017.Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs

Field Programmable Gate Arrays (FPGAs) II

This Edited Volume Field Programmable Gate Arrays (FPGAs) II is a collection of reviewed and relevant research chapters, offering a comprehensive overview of recent developments in the field of Computer and Information Science. The book comprises single chapters authored by various researchers and edited by an expert active in the Computer and Information Science research area. All chapters are complete in itself but united under a common research study topic. This publication aims at providing a thorough overview of the latest research efforts by international authors on Computer and Information Science, and open new possible research paths for further novel developments

Microscale controlled continuous cell culture

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 489-500).Measurements of metabolic and cellular activity through substrate and product interactions are highly dependent on environmental conditions and cellular metabolic state. For such experiments to be feasible, continuous cultures are utilized to ensure consistent conditions. However, since medium must be replenished every cell doubling time, costs can be prohibitive in large reactors. An integrated microscale bioreactor with built-in fluid metering and environmental control will enable programmed experiments capable of generating reproducible data routinely. This work develops an instrument capable of supporting automated microscale continuous culture experiments. The instrument consists of a plastic-PDMS device capable of continuous flow reactions without volume drift. A novel bonding process is invented to fabricate devices with chemically stable interfaces against water, acids, and bases. We introduce a direct CNC machining and chemical bonding fabrication process for production of fluidic devices with a 1 mL working volume, high oxygen transfer rate (kLa ~ 0.025 s-1), fast mixing (2 s), accurate flow control (± 18 nL), and closed loop control over temperature, cell density, oxygen, and pH. Providing control over environmental parameters allows the system to perform different types of cell culture on a single device, such as batch, fed-batch, chemostat, and turbidostat continuous culture. Validation experiments demonstrate that cells can be grown to high optical densities (OD = 50) and production of commercially relevant chemicals such as DNA vaccines are comparable to large scale bench fermentations. Continuous cultures are also demonstrated without contamination for 3 weeks in a single device and both steady state and dynamically controlled conditions are possible, allowing observations of cell metabolic dynamics.by Kevin Shao-Kwan Lee.Ph.D

Générateur distribué d'horloge pour puces globalement et localement synchrones de grande taille

This thesis addresses the problem of global synchronization of large system on chip (SoC). It focuses on the study of an alternative clock generation technique to conventional clock distribution and asynchronous communication. It allows implementation of highly reliable synchronous circuit. My PhD project aims to study and implement a large network (10x10) of all digital phase-locked loop (ADPLL), containing 100 nodes generating a clock for each local digital circuitry. The prototype was implemented on silicon generating clocks in the range 903-1161 MHz. It highlights a maximum phase error of less than 40 ps between two clocks in any neighboring zones. Another important result is the analysis of phase error between two non-neighboring oscillators in distance. By studying an FPGA prototype of the network, we obtained that maximum phase error at steady state between any clock signal and the reference signal is less than three steps of the PFD quantification steps. In order to validate the performance of synchronization in ASIC, we designed an on-chip clocking error measurement circuit. This circuit has a low rate for the off-chip readout (several MHz), and a high resolution (+-2.5 ps). Reconfigurability is another attractive feature. We have explored this feature and proposed a novel topology with different configurations for nodes on the border and in the kernel of the network. This topology has an advantage in prohibiting phase error propagation and reflection.Cette thèse aborde le problème de la synchronisation globale de grand système sur puce (SoC). Il est centré sur l'étude d'une technique de remplacement de la distribution d'horloge classique et d'une communication asynchrone. Il permet la mise en œuvre de circuit synchrone très fiable. Mon projet de thèse vise à étudier et mettre en œuvre un vaste réseau (10x10) de boucle à verrouillage de phase tous numérique (ADPLL), contenant 100 nœuds générant une horloge pour chaque circuit numérique local. Le prototype a été réalisé sur les horloges de génération de silicium dans la gamme de 903-1161 MHz. Elle met en évidence une erreur de phase maximale de moins de 40 ps entre deux horloges dans toutes les zones voisines. Un autre résultat important est l'analyse de l'erreur de phase entre les deux oscillateurs non-voisins dans la distance. En étudiant un prototype FPGA du réseau, on a obtenu que l'erreur de phase maximale à l'état d'équilibre entre un signal d'horloge et le signal de référence est inférieur à trois étapes des étapes de quantification PFD. Afin de valider les performances de la synchronisation dans ASIC, nous avons conçu un circuit d'une erreur de mesure sur la puce d'horloge. Ce circuit a un taux faible de la lecture hors puce (quelques MHz), et une résolution élevée (+ -2,5 ps). Reconfiguration constitue une autre caractéristique intéressante. Nous avons exploré cette fonction et a proposé une nouvelle topologie avec des configurations différentes pour les nœuds sur la frontière et dans le noyau du réseau. Cette topologie présente un avantage en interdisant la propagation des erreurs de phase et de réflexion

Implementation of Offset Pulse Position Modulation

Optical fibre systems have played a key role in making possible the extraordinary growth in world-wide communications that has occurred in the last 25 years, and are vital in enabling the proliferating use of the Internet. Its high bandwidth capabilities, low attenuation characteristics, low cost, and immunity from the many disturbances that can afflict electrical wires and wireless communication links make it ideal for gigabit transmission and a major building block in the telecommunication infrastructure. The main concern of this thesis is a full and detailed investigation and implementation of the Offset Pulse Position Modulation (Offset PPM) communication system. Novel work is carried out for applying Offset PPM over an optical communication channel theoretically and experimentally to examine the system performance. An Offset PPM encoder and decoder were implemented to code Pulse Code Modulation (PCM) format into Offset PPM format and to decode back the Offset PPM to PCM. The first paradigm of implementation was implemented using electronic components. A further investigation took place on the Offset PPM associated output. Computer programming and simulation using the VHSIC Hardware Description Language (VHDL) of this PPM code was considered and comparison with previous theoretical results presented. The received Offset PPM signal returned back to its original input PCM form without errors. Successful VHDL and Field Programmable Gate Array (FPGA) implementation using Altera Quartus II of Offset PPM encoder and decoder as a single system has been presented in the study. An FPGA embedded Bit Error Rate (BER) test device has also been implemented for sensitivity measurements purposes and all the designs have been tested successfully with back-to-back testing. Results show that Offset PPM is an advantageous PPM code for optic communication. Furthermore, the system has achieved a very high data rate of 50 Mb/s without an optical communication set. An optical communication system (transmitter/receiver) over POF was developed and the Offset PPM scheme was investigated through this optical channel. Results show that the Offset PPM sequence transferred through the optic system without being altered. In addition, this implementation is optimised PPM coding; the system is working perfectly with up to 10 Mb/s with 10-12 BER based on the limitations of the optical communication set. All the results and analyses indicate that Offset PPM is an ideal alternative to be considered for highly dispersive optical channels, and performance evaluation for higher bandwidths also favourably compares to existing coding schemes

Industrial and Technological Applications of Power Electronics Systems

The Special Issue "Industrial and Technological Applications of Power Electronics Systems" focuses on: - new strategies of control for electric machines, including sensorless control and fault diagnosis; - existing and emerging industrial applications of GaN and SiC-based converters; - modern methods for electromagnetic compatibility. The book covers topics such as control systems, fault diagnosis, converters, inverters, and electromagnetic interference in power electronics systems. The Special Issue includes 19 scientific papers by industry experts and worldwide professors in the area of electrical engineering

A configurable vector processor for accelerating speech coding algorithms

The growing demand for voice-over-packer (VoIP) services and multimedia-rich applications has made increasingly important the efficient, real-time implementation of low-bit rates speech coders on embedded VLSI platforms. Such speech coders are designed to substantially reduce the bandwidth requirements thus enabling dense multichannel gateways in small form factor. This however comes at a high computational cost which mandates the use of very high performance embedded processors. This thesis investigates the potential acceleration of two major ITU-T speech coding algorithms, namely G.729A and G.723.1, through their efficient implementation on a configurable extensible vector embedded CPU architecture. New scalar and vector ISAs were introduced which resulted in up to 80% reduction in the dynamic instruction count of both workloads. These instructions were subsequently encapsulated into a parametric, hybrid SISD (scalar processor)–SIMD (vector) processor. This work presents the research and implementation of the vector datapath of this vector coprocessor which is tightly-coupled to a Sparc-V8 compliant CPU, the optimization and simulation methodologies employed and the use of Electronic System Level (ESL) techniques to rapidly design SIMD datapaths

Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing