CMOS dual-modulus prescaler design for RF frequency synthesizer applications.

Ng Chong Chon.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 100-103).Abstract in English and Chinese.摘要 --- p.iiiAcknowledgments --- p.ivContents --- p.viList of Figures --- p.ixList of Tables --- p.xiiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Thesis Organization --- p.4Chapter Chapter 2 --- DMP Architecture --- p.6Chapter 2.1 --- Conventional DMP --- p.6Chapter 2.1.1 --- Operating Principle --- p.7Chapter 2.1.2 --- Disadvantages --- p.10Chapter 2.2 --- Pre-processing Clock Architecture --- p.10Chapter 2.2.1 --- Operating Principle --- p.11Chapter 2.2.2 --- Advantages and Disadvantages --- p.12Chapter 2.3 --- Phase-switching Architecture --- p.13Chapter 2.3.1 --- Operating Principle --- p.13Chapter 2.3.2 --- Advantages and Disadvantages --- p.14Chapter 2.4 --- Summary --- p.15Chapter Chapter 3 --- Full-Speed Divider Design --- p.16Chapter 3.1 --- Introduction --- p.16Chapter 3.2 --- Working Principle --- p.16Chapter 3.3 --- Design Issues --- p.18Chapter 3.4 --- Device Sizing --- p.19Chapter 3.5 --- Layout Considerations --- p.20Chapter 3.6 --- Input Sensitivity --- p.22Chapter 3.7 --- Modeling --- p.24Chapter 3.8 --- Review on Different Divider Designs --- p.28Chapter 3.8.1 --- Divider with Dynamic-Loading Technique --- p.28Chapter 3.8.2 --- Divider with Negative-Slew Technique --- p.30Chapter 3.8.3 --- LC Injection-Locked Frequency Divider --- p.32Chapter 3.8.4 --- Dynamic True Single Phase Clock Frequency Divider --- p.34Chapter 3.9 --- Summary --- p.42Chapter Chapter 4 --- 3V 900MHz Low Noise DMP --- p.43Chapter 4.1 --- Introduction --- p.43Chapter 4.2 --- Proposed DMP Topology --- p.46Chapter 4.3 --- Circuit Design and Implementation --- p.49Chapter 4.4 --- Simulation Results --- p.51Chapter 4.5 --- Summary --- p.53Chapter Chapter 5 --- 1.5V 2.4GHz Low Power DMP --- p.54Chapter 5.1 --- Introduction --- p.54Chapter 5.2 --- Proposed DMP Topology --- p.56Chapter 5.3 --- Circuit Design and Implementation --- p.59Chapter 5.3.1 --- Divide-by-4 stage --- p.59Chapter 5.3.2 --- TSPC dividers --- p.63Chapter 5.3.3 --- Phase-selection Network --- p.63Chapter 5.3.4 --- Mode-control Logic --- p.64Chapter 5.3.5 --- Duty-cycle Transformer --- p.65Chapter 5.3.6 --- Glitch Problem --- p.66Chapter 5.3.7 --- Phase-mismatch Problem --- p.70Chapter 5.4 --- Simulation Results --- p.70Chapter 5.5 --- Summary --- p.74Chapter Chapter 6 --- 1.5V 2.4GHz Wideband DMP --- p.75Chapter 6.1 --- Introduction --- p.75Chapter 6.2 --- Proposed DMP Architecture --- p.75Chapter 6.3 --- Divide-by-4 Stage --- p.76Chapter 6.3.1 --- Current-switch Combining --- p.76Chapter 6.3.2 --- Capacitive Load Reduction --- p.77Chapter 6.4 --- Simulation Results --- p.81Chapter 6.5 --- Summary --- p.83Chapter Chapter 7 --- Experimental Results --- p.84Chapter 7.1 --- Introduction --- p.84Chapter 7.2 --- Equipment Setup --- p.84Chapter 7.3 --- Measurement Results --- p.85Chapter 7.3.1 --- 3V 900GHz Low Noise DMP --- p.85Chapter 7.3.2 --- 1.5V 2.4GHz Low Power DMP --- p.88Chapter 7.3.3 --- 1.5V 2.4GHz Wideband DMP --- p.93Chapter 7.3 --- Summary --- p.96Chapter Chapter 8 --- Conclusions and Future Works --- p.98Chapter 8.1 --- Conclusions --- p.98Chapter 8.2 --- Future Works --- p.99References --- p.100Publications --- p.10

Review of Clocked Storage Elements in Digital Circuit Design

Storage of digital circuit is "state" or memory. These are called sequential circuits. The most fundamental sequential circuit type that we will ponder is known as the Flip-Flop. It is ponder four distinct assortments of these gadgets and their utilization in registers and register documents, which can be considered as one type of on– CPU memory. The traditional memory, called RAM, is ordinarily not on the CPU chip. Regular Slam and its assortments, including RAM, ROM, SRAM, Measure, and SDRAM. True single-phase clock (TSPC) method of reasoning has found wide use in advanced plan. At first as a quick topology, the TSPC structure in like manner eats up less power and includes less areas than various systems. In flip-flop plan only a single transistor is being clocked by short heartbeat get ready which is known as True Single Phase Clocking (TSPC) flip-flop

Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications

In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect current-matching characteristics, wide output range, no glitch output current, and no jump output voltage. In order to verify such operation, circuit simulation is performed using 0.18 μm CMOS process parameters

Integrated radio frequency synthetizers for wireless applications

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe

Design of frequency synthesizers for short range wireless transceivers

The rapid growth of the market for short-range wireless devices, with standards such as Bluetooth and Wireless LAN (IEEE 802.11) being the most important, has created a need for highly integrated transceivers that target drastic power and area reduction while providing a high level of integration. The radio section of the devices designed to establish communications using these standards is the limiting factor for the power reduction efforts. A key building block in a transceiver is the frequency synthesizer, since it operates at the highest frequency of the system and consumes a very large portion of the total power in the radio. This dissertation presents the basic theory and a design methodology of frequency synthesizers targeted for short-range wireless applications. Three different examples of synthesizers are presented. First a frequency synthesizer integrated in a Bluetooth receiver fabricated in 0.35μm CMOS technology. The receiver uses a low-IF architecture to downconvert the incoming Bluetooth signal to 2MHz. The second synthesizer is integrated within a dual-mode receiver capable of processing signals of the Bluetooth and Wireless LAN (IEEE 802.11b) standards. It is implemented in BiCMOS technology and operates the voltage controlled oscillator at twice the required frequency to generate quadrature signals through a divide-by-two circuit. A phase switching prescaler is featured in the synthesizer. A large capacitance is integrated on-chip using a capacitance multiplier circuit that provides a drastic area reduction while adding a negligible phase noise contribution. The third synthesizer is an extension of the second example. The operation range of the VCO is extended to cover a frequency band from 4.8GHz to 5.85GHz. By doing this, the synthesizer is capable of generating LO signals for Bluetooth and IEEE 802.11a, b and g standards. The quadrature output of the 5 - 6 GHz signal is generated through a first order RC - CR network with an automatic calibration loop. The loop uses a high frequency phase detector to measure the deviation from the 90° separation between the I and Q branches and implements an algorithm to minimize the phase errors between the I and Q branches and their differential counterparts

Circuit designs for low-power and SEU-hardened systems

The desire to have smaller and faster portable devices is one of the primary motivations for technology scaling. Though advancements in device physics are moving at a very good pace, they might not be aggressive enough for now-a-day technology scaling trends. As a result, the MOS devices used for present day integrated circuits are pushed to the limit in terms of performance, power consumption and robustness, which are the most critical criteria for almost all applications. Secondly, technology advancements have led to design of complex chips with increasing chip densities and higher operating speeds. The design of such high performance complex chips (microprocessors, digital signal processors, etc) has massively increased the power dissipation and, as a result, the operating temperatures of these integrated circuits. In addition, due to the aggressive technology scaling the heat withstanding capabilities of the circuits is reducing, thereby increasing the cost of packaging and heat sink units. This led to the increase in prominence for smarter and more robust low-power circuit and system designs. Apart from power consumption, another criterion affected by technology scaling is robustness of the design, particularly for critical applications (security, medical, finance, etc). Thus, the need for error free or error immune designs. Until recently, radiation effects were a major concern in space applications only. With technology scaling reaching nanometer level, terrestrial radiation has become a growing concern. As a result Single Event Upsets (SEUs) have become a major challenge to robust designs. Single event upset is a temporary change in the state of a device due to a particle strike (usually from the radiation belts or from cosmic rays) which may manifest as an error at the output. This thesis proposes a novel method for adaptive digital designs to efficiently work with the lowest possible power consumption. This new technique improves options in performance, robustness and power. The thesis also proposes a new dual data rate flipflop, which reduces the necessary clock speed by half, drastically reducing the power consumption. This new dual data rate flip-flop design culminates in a proposed unique radiation hardened dual data rate flip-flop, Firebird\u27. Firebird offers a valuable addition to the future circuit designs, especially with the increasing importance of the Single Event Upsets (SEUs) and power dissipation with technology scaling.\u2

A high-frequency quad-modulus prescaler for fractional-N frequency synthesizer

Master'sMASTER OF ENGINEERIN

Clock Generator Circuits for Low-Power Heterogeneous Multiprocessor Systems-on-Chip

In this work concepts and circuits for local clock generation in low-power heterogeneous multiprocessor systems-on-chip (MPSoCs) are researched and developed. The targeted systems feature a globally asynchronous locally synchronous (GALS) clocking architecture and advanced power management functionality, as for example fine-grained ultra-fast dynamic voltage and frequency scaling (DVFS). To enable this functionality compact clock generators with low chip area, low power consumption, wide output frequency range and the capability for ultra-fast frequency changes are required. They are to be instantiated individually per core. For this purpose compact all digital phase-locked loop (ADPLL) frequency synthesizers are developed. The bang-bang ADPLL architecture is analyzed using a numerical system model and optimized for low jitter accumulation. A 65nm CMOS ADPLL is implemented, featuring a novel active current bias circuit which compensates the supply voltage and temperature sensitivity of the digitally controlled oscillator (DCO) for reduced digital tuning effort. Additionally, a 28nm ADPLL with a new ultra-fast lock-in scheme based on single-shot phase synchronization is proposed. The core clock is generated by an open-loop method using phase-switching between multi-phase DCO clocks at a fixed frequency. This allows instantaneous core frequency changes for ultra-fast DVFS without re-locking the closed loop ADPLL. The sensitivity of the open-loop clock generator with respect to phase mismatch is analyzed analytically and a compensation technique by cross-coupled inverter buffers is proposed. The clock generators show small area (0.0097mm2 (65nm), 0.00234mm2 (28nm)), low power consumption (2.7mW (65nm), 0.64mW (28nm)) and they provide core clock frequencies from 83MHz to 666MHz which can be changed instantaneously. The jitter performance is compliant to DDR2/DDR3 memory interface specifications. Additionally, high-speed clocks for novel serial on-chip data transceivers are generated. The ADPLL circuits have been verified successfully by 3 testchip implementations. They enable efficient realization of future low-power MPSoCs with advanced power management functionality in deep-submicron CMOS technologies.In dieser Arbeit werden Konzepte und Schaltungen zur lokalen Takterzeugung in heterogenen Multiprozessorsystemen (MPSoCs) mit geringer Verlustleistung erforscht und entwickelt. Diese Systeme besitzen eine global-asynchrone lokal-synchrone Architektur sowie Funktionalität zum Power Management, wie z.B. das feingranulare, schnelle Skalieren von Spannung und Taktfrequenz (DVFS). Um diese Funktionalität zu realisieren werden kompakte Taktgeneratoren benötigt, welche eine kleine Chipfläche einnehmen, wenig Verlustleitung aufnehmen, einen weiten Bereich an Ausgangsfrequenzen erzeugen und diese sehr schnell ändern können. Sie sollen individuell pro Prozessorkern integriert werden. Dazu werden kompakte volldigitale Phasenregelkreise (ADPLLs) entwickelt, wobei eine bang-bang ADPLL Architektur numerisch modelliert und für kleine Jitterakkumulation optimiert wird. Es wird eine 65nm CMOS ADPLL implementiert, welche eine neuartige Kompensationsschlatung für den digital gesteuerten Oszillator (DCO) zur Verringerung der Sensitivität bezüglich Versorgungsspannung und Temperatur beinhaltet. Zusätzlich wird eine 28nm CMOS ADPLL mit einer neuen Technik zum schnellen Einschwingen unter Nutzung eines Phasensynchronisierers realisiert. Der Prozessortakt wird durch ein neuartiges Phasenmultiplex- und Frequenzteilerverfahren erzeugt, welches es ermöglicht die Taktfrequenz sofort zu ändern um schnelles DVFS zu realisieren. Die Sensitivität dieses Frequenzgenerators bezüglich Phasen-Mismatch wird theoretisch analysiert und durch Verwendung von kreuzgekoppelten Taktverstärkern kompensiert. Die hier entwickelten Taktgeneratoren haben eine kleine Chipfläche (0.0097mm2 (65nm), 0.00234mm2 (28nm)) und Leistungsaufnahme (2.7mW (65nm), 0.64mW (28nm)). Sie stellen Frequenzen von 83MHz bis 666MHz bereit, welche sofort geändert werden können. Die Schaltungen erfüllen die Jitterspezifikationen von DDR2/DDR3 Speicherinterfaces. Zusätzliche können schnelle Takte für neuartige serielle on-Chip Verbindungen erzeugt werden. Die ADPLL Schaltungen wurden erfolgreich in 3 Testchips erprobt. Sie ermöglichen die effiziente Realisierung von zukünftigen MPSoCs mit Power Management in modernsten CMOS Technologien

Analysis and Design of Radio Frequency Integrated Circuits for Breast Cancer Radar Imaging in CMOS Technology

Breast cancer is by far the most incident tumor among female population. Early stage prevention is a key factor in delivering long term survival of breast cancer patients. X-ray mammography is the most commonly used diagnostic technique to detect non-palpable tumors. However, 10-30% of tumors are missed by mammography and ionizing radiations together with breast compression do not lead to comfort in patient treatment. In this context, ultrawideband microwave radar technology is an attractive alternative. It relies on the dielectric contrast of normal and malignant tissues at microwave frequencies to detect and locate tumors inside the breast. This work presents the analysis and design of radio frequency integrated circuits for breast cancer imaging in CMOS technology. The first part of the thesis concerns the system analysis. A behavioral model of two different transceiver architectures for UWB breast cancer imaging employing a SFCW radar system are presented. A mathematical model of the direct conversion and super heterodyne architectures together with a numerical breast phantom are developed. FDTD simulations data are used to on the behavioral model to investigate the limits of both architectures from a circuit-level point of view. Insight is given into I/Q phase inaccuracies and their impact on the quality of the final reconstructed images. The result is that the simplicity of the direct conversion architecture makes the receiver more robust toward the critical impairments for this application. The second part of the thesis is dedicated to the circuit design. The main achievement is a 65nm CMOS 2-16GHz stepped frequency radar transceiver for medical imaging. The RX features 36dB conversion gain, >29dBm compression point, 7dB noise figure, and 30Hz 1/f noise corner. The TX outputs 14dBm with >40dBc harmonic rejection and <109dBc/Hz phase noise at 1MHz offset. Overall power dissipation is 204mW from 1.2V supply. The radar achieves 3mm resolution within the body, and 107dB dynamic range, a performance enabling the use for breast cancer diagnostic imaging. To further assess the capabilities of the proposed radar, a physical breast phantom was synthesized and two targets mimicking two tumors were buried inside the breast. The targets are clearly identified and correctly located, effectively proving the performance of the designed radar as a possible tool for breast cancer detection