CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso

High Linearity Millimeter Wave Power Amplifiers with Novel Linearizer Techniques

Millimeter-wave communications have experienced phenomenal growth in recent years when limited frequency spectrum is occupied by the ever-developing communication services. The power amplifier, as the key component in the transmitter/receiver module of communication systems, affects performance of the whole system directly and receives much attention. For minimized distortion and optimum system performance, the non-constant en- velope modulation schemes used in communication systems have challenging requirements on linearity. As linearity is related to communication quality directly, several linearization techniques, such as predistortion and feedforward, are applied to power amplifier design. Predistortion method has the advantages over other techniques in relatively simple struc- ture and reasonable linearity improvement. But current predistortion circuits have quite limited performance improvement and relatively large insertion loss, which indicate the need for further research. In most of millimeter-wave amplifier design, great effort has been spent on output power or gain, while linearity is often ignored. As almost all the predistortion circuits operate at the RF frequencies, the linearized millimeter-wave com- munication circuit is still relatively immature and very challenging. This project is dedicated to solve the linearity problem faced by millimeter-wave power amplifier in communication systems, which lacks of e®ective techniques in this field. Linearity improvement with the predistortion method will be the key issue in this project and some original ideas for predistortion circuit design will be applied to millimeter-wave amplifiers. In this thesis, several predistortion circuits with novel structure were proposed, which provide a new approach for linearity improvement for millimeter-wave power am- plifier. A millimeter-wave power ampli¯er for LMDS applications built on GaAs pHEMT technology was developed to a high engineering standard, which works as the test bench for linearization. Actual operation and parasitic elements at tens of gigahertz have been taken into consideration during the design. Firstly, two novel predistorter structures based on the amplifier were proposed, one is based on an amplifier with a fixed bias circuit and the other is based on an amplifier with a nonlinear signal dependant bias circuit. These novel structures can improve the linearity while improving other metrics simultaneously, which can effectively solve the problem of insertion loss faced by the conventional structures. Besides this, an original predistortion circuit design methodology derived from frequency to signal amplitude transformation was proposed. Based on this methodology, several transfer functions were proposed and related predistortion circuits were built to linearize the power amplifier. As this methodology is quite different from the traditional approach, it can improve the linearity signifficantly while other metrics are affected slightly and has a broad prospect for application

High Linearity Millimeter Wave Power Amplifiers with Novel Linearizer Techniques

Millimeter-wave communications have experienced phenomenal growth in recent years when limited frequency spectrum is occupied by the ever-developing communication services. The power amplifier, as the key component in the transmitter/receiver module of communication systems, affects performance of the whole system directly and receives much attention. For minimized distortion and optimum system performance, the non-constant en- velope modulation schemes used in communication systems have challenging requirements on linearity. As linearity is related to communication quality directly, several linearization techniques, such as predistortion and feedforward, are applied to power amplifier design. Predistortion method has the advantages over other techniques in relatively simple struc- ture and reasonable linearity improvement. But current predistortion circuits have quite limited performance improvement and relatively large insertion loss, which indicate the need for further research. In most of millimeter-wave amplifier design, great effort has been spent on output power or gain, while linearity is often ignored. As almost all the predistortion circuits operate at the RF frequencies, the linearized millimeter-wave com- munication circuit is still relatively immature and very challenging. This project is dedicated to solve the linearity problem faced by millimeter-wave power amplifier in communication systems, which lacks of e®ective techniques in this field. Linearity improvement with the predistortion method will be the key issue in this project and some original ideas for predistortion circuit design will be applied to millimeter-wave amplifiers. In this thesis, several predistortion circuits with novel structure were proposed, which provide a new approach for linearity improvement for millimeter-wave power am- plifier. A millimeter-wave power ampli¯er for LMDS applications built on GaAs pHEMT technology was developed to a high engineering standard, which works as the test bench for linearization. Actual operation and parasitic elements at tens of gigahertz have been taken into consideration during the design. Firstly, two novel predistorter structures based on the amplifier were proposed, one is based on an amplifier with a fixed bias circuit and the other is based on an amplifier with a nonlinear signal dependant bias circuit. These novel structures can improve the linearity while improving other metrics simultaneously, which can effectively solve the problem of insertion loss faced by the conventional structures. Besides this, an original predistortion circuit design methodology derived from frequency to signal amplitude transformation was proposed. Based on this methodology, several transfer functions were proposed and related predistortion circuits were built to linearize the power amplifier. As this methodology is quite different from the traditional approach, it can improve the linearity signifficantly while other metrics are affected slightly and has a broad prospect for application

Bifurcations and synchronization using an integrated programmable chaotic circuit

This paper presents a CMOS chip which can act as an autonomous stand-alone unit to generate different real-time chaotic behaviors by changing a few external bias currents. In particular, by changing one of these bias currents, the chip provides different examples of a period-doubling route to chaos. We present experimental orbits and attractors, time waveforms and power spectra measured from the chip. By using two chip units, experiments on synchronization can be carried out as well in real-time. Measurements are presented for the following synchronization schemes: linear coupling, drive-response and inverse system. Experimental statistical characterizations associated to these schemes are also presented. We also outline the possible use of the chip for chaotic encryption of audio signals. Finally, for completeness, the paper includes also a brief description of the chip design procedure and its internal circuitry

Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits

This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs). Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB. The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date

Optimal Area Allocation for Yield Enhancement of DAC

Práce seznamuje s metodami návrhu pro zvýšení výtěžnosti a omezení chyb ve shodných strukturách. Systematické a náhodné chyby jsou shledány zdrojem neshod mezi strukturami. Je představen model náhodných chyb za využití log-normálové hustoty pravděpodobnosti. Pomocí nové metodologie založené na celočíselném pogramování (celočíselné optimalizaci) je navržena optimalizace parametrické výtěžnosti integrovaných obvodů. Je představen algoritmus generování optimální topologie. Topologie je demonstrována na R-2R D/A převodníku a výsledky jsou porovnány s jivým řešením.Recent research in yield enhancement techniques and mitigation of device mismatch is presented. Systematic and random mismatch is studied and identified as the cause of device mismatch. Model based on log-normal PDF is introduced. Optimization of IC parameter yield is suggested and conducted with help of a new methodology based on mathematical programming. An algorithm for the impact based area allocation of critical matched devices is shown as well as algorithms for common centroid layout of different sized devices. Newly developed algorithms are presented on binary weighted R-2R DAC as it is a common IC and comparison to other solutions is given

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process