A testability metric for path delay faults and its application

Abstract — In this paper, we propose a new testability metric for path delay faults. The metric is computed efficiently using a non-enumerative algorithm. It has been validated through extensive experiments and the results indicate a strong correlation between the proposed metric and the path delay fault testability of the circuit. We further apply this metric to derive a path delay fault test application scheme for scan-based BIST. The selection of the test scheme is guided by the proposed metric. The experimental results illustrate that the derived test application scheme can achieve a higher path delay fault coverage in scan-based BIST. Because of the effectiveness and efficient computation of this metric, it can be used to derive other design-for-testability techniques for path delay faults. I

A novel path delay fault simulator using binary logic

A novel path delay fault simulator for combinational logic circuits which is capable of detecting both robust and nonrobust paths is presented. Particular emphasis has been given for the use of binary logic rather than the multiple-valued logic as used in the existing simulators which contributes to the reduction of the overall complexity of the algorithm. A rule based approach has been developed which identifies all robust and nonrobust paths tested by a two-pattern test <V1,V2>, while backtracing from the POs to PIs in a depth-first manner. Rules are also given to find probable glitches and to determine how they propagate through the circuit, which enables the identification of nonrobust paths. Experimental results on several ISCAS'85 benchmark circuits demonstrate the efficiency of the algorithm

Optimization of Constrained Random Verification using Machine Learning

University of Minnesota M.S.E.E. thesis. 2018. Major: Electrical Engineering. Advisor: Gerald Sobelman. 1 computer file (PDF); 69 pages.Constrained random simulations play a critical role in Design Verification today. But the effort and time spent to manually update the input constraints, analyzing and prioritizing the unverified features in the design, significantly affect the time taken to converge to the coverage goal. This research work focuses on the optimization of constrained random verification using Machine Learning algorithms, in a coverage-driven simulation using a Universal Verification Methodology (UVM) framework. The optimization will greatly reduce the time a simulation takes to converge to the coverage goal. This research work targets automating the update of the constraints during runtime, abstracting the need for understanding the design to verify it, using Machine Learning. The verification environment is further optimized using techniques including Objective Function, Rewinding and Dynamic Seed Manipulation. The enhanced environment resolves the limitations of the previous efforts at employing these techniques, optimizing the scalability of the environment and enhancing its compatibility at verifying complex combinational designs and sequential designs including Finite State Machines (FSMs). The optimized verification environment comprises of a SystemVerilog testbench which interfaces and interacts with a TCL environment. The methodology has been empirically demonstrated, with remarkable results showing its superior quality in terms of faster automated coverage closure, efficient final stimulus solution and proposed higher quality of coverage. Multiple Machine Learning algorithms, including a Linear Regression Model and Artificial Neural Networks, have been employed to scale the compatibility of the verification environment, making it capable of autonomously verifying designs of varied behavior. Adequate simulation results to demonstrate the same have been presented in the report

Space Communications: Theory and Applications. Volume 3: Information Processing and Advanced Techniques. A Bibliography, 1958 - 1963

Annotated bibliography on information processing and advanced communication techniques - theory and applications of space communication

PERFORMANCE EVALUATION OF CROSS-LAYER DESIGN WITH DISTRIBUTED AND SEQUENTIAL MAPPING SCHEME FOR VIDEO APPLICATION OVER IEEE 802.11E

The rapid development of wireless communication imposes several challenges to support QoS for real-time multimedia applications such as video stream applications. Researchers tackled these challenges from different points of view including the semantics of the video to achieve better QoS requirements. The main goal of this research is to design a UDP protocol to realize a distributed sequential mapping scheme (DSM) with a cross-layer design and evaluate its accuracy under different network conditions. In DSM, the perceived quality of a multi-layer video is addressed by mapping each video layer into channel resources represented as queues or access categories (ACs) existing in IEEE 802.11e MAC layer. This research work further investigates the efficiency of this scheme with actual implementation and thorough simulation experiments. The experiments reported the efficiency of this scheme with the presence of different composite traffic models covering most known traffic scenarios using Expected Reconstructed Video Layers (ERVL) and packet loss rate as accuracy measures. This research work also investigates the accuracy of calculating the ERVL compared to its value using actual readings of layers drop rate. The effect of changing the ACs queue size on the ERVL is studied. The use of this scheme shows zero-drop in the base layer in almost all scenarios where no ongoing traffic is presented except that the testing video sessions between nodes. In these experiments, the ERVL continuously reported high values for the number of expected reconstructed video layers. While these values dramatically vary when introducing ongoing different composite traffic models together with the testing video sessions between nodes. Finally, a 40% increase in the ACs queue size shows significant improvement on ERVL while an increase of the queue size beyond this value has very little significance on ERVL