Application of the averaged model of the diode-transistor switch for modelling characteristics of a boost converter with an IGBT

DC-DC converters are popular switch-mode electronic circuits used in power supply systems of many electronic devices. Designing such converters requires reliable computation methods and models of components contained in these converters, allowing for accurate and fast computations of their characteristics. In the paper, a new averaged model of a diode-transistor switch containing an IGBTis proposed. The form of the developed model is presented. Its accuracy is verified by comparing the computed characteristics of the boost converter with the characteristics computed in SPICE using a transient analysis and literature models of a diode and an IGBT. The obtained results of computations proved the usefulness of the proposed model

Application of the averaged model of the diode-transistor switch for modelling characteristics of a boost converter with an IGBT

DC-DC converters are popular switch-mode electronic circuits used in power supply systems of many electronic devices. Designing such converters requires reliable computation methods and models of components contained in these converters, allowing for accurate and fast computations of their characteristics. In the paper, a new averaged model of a diode-transistor switch containing an IGBTis proposed. The form of the developed model is presented. Its accuracy is verified by comparing the computed characteristics of the boost converter with the characteristics computed in SPICE using a transient analysis and literature models of a diode and an IGBT. The obtained results of computations proved the usefulness of the proposed model

Analysis of design strategies for RF ESD problems in CMOS circuits

This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip

Design and Control of Power Converters 2020

In this book, nine papers focusing on different fields of power electronics are gathered, all of which are in line with the present trends in research and industry. Given the generality of the Special Issue, the covered topics range from electrothermal models and losses models in semiconductors and magnetics to converters used in high-power applications. In this last case, the papers address specific problems such as the distortion due to zero-current detection or fault investigation using the fast Fourier transform, all being focused on analyzing the topologies of high-power high-density applications, such as the dual active bridge or the H-bridge multilevel inverter. All the papers provide enough insight in the analyzed issues to be used as the starting point of any research. Experimental or simulation results are presented to validate and help with the understanding of the proposed ideas. To summarize, this book will help the reader to solve specific problems in industrial equipment or to increase their knowledge in specific fields

The potential of SiC Cascode JFETs in electric vehicle traction inverters

The benefits of implementing SiC devices in EV powertrains has been widely reported in various studies. New generations of SiC devices including planar MOSFETs, trench MOSFETs and more recently, cascode JFETs have been released by various manufacturers. SiC cascode devices comprise of low voltage silicon MOSFETs for gate driving and high voltage depletion mode SiC JFETs for voltage blocking. These devices are particularly interesting because it avoids the known reliability issues of SiC gate oxide traps resulting in threshold voltage drift. In this paper, an EV powertrain is simulated using experimental measurements of conduction and switching energies of various SiC devices including 650V trench, 900V planar and 650V cascode JFETs. Unlike previous papers where losses are calculated using models based on datasheet parameters, here static and dynamic measurements on the power devices at different currents and temperatures are used to calculate losses over simulated driving cycles. Field-stop IGBTs are also evaluated. The 3-phase 2-level inverter model is electrothermal by accounting for the measured temperature dependence of the losses and uses accurate thermal networks derived from datasheets. Converter efficiency and thermal performance are compared for each device technology. Results show that SiC cascode JFETs have great potential in EV powertrain applications

Study and analysis of state-of-the-art FCS-MPC strategies for thermal regulation of power converters

La degradación en los convertidores de potencia basados en silicio, enmarcados en sistemas de tracción eléctrica y fuentes de energías renovables, es un tema de estudio de especial interés para aquellas aplicaciones donde los fallos amenazan la seguridad de personas o donde el mantenimiento es particularmente costoso. Motivado por la influencia de los fallos en IGBTs sobre los fallos habituales en los convertidores de potencia comunes, este trabajo utiliza la herramienta software PLECS como marco de trabajo para la simulación de algoritmos de control predictivo basado en modelo con conjunto finito de acciones de control (FCS-MPC) que pretenden -simultáneamente a conseguir el seguimiento eléctrico- extender directa o indirectamente la vida útil de los IGBTs. El trabajo se enfoca principalmente a la simulación en ordenador de los algoritmos controlando un inversor de dos niveles conectado a una carga RL. Además, pretende también introducir la implementación de éstos sobre un microcontrolador para su estudio controlando el inversor simulado en la plataforma PLECS RT Box 1, con el fin último de poder desarrollar validaciones de los controladores basadas en técnicas Hardware-In-the-Loop.Degradation of silicon-based power electronics converters in traction and renewable energy systems is a topic of interest particularly where module failure supposes a safety threat or where maintenance becomes especially expensive. Motivated by the influence of IGBT aging in usual power converters, this work uses the software tool PLECS as framework to simulate Finite Control Set Model Predictive Control (FCSMPC) algorithms that, simultaneously to achieving a certain current tracking, aim to directly or indirectly extend IGBTs’ lifetime. Whilst the work focuses on offline simulation of the algorithms on PLECS, it also targets to pave the way to implement algorithms in a micro-controller and to study how they control a two-level inverter connected to a RL load simulated on a PLECS RT Box 1 platform. The ultimate goal is to develop validations based on Hardware-In-the-Loop techniques of the control algorithms.Universidad de Sevilla. Máster Universitario en Ingeniería Electrónica, Robótica y Automátic

Fast switching SiC cascode JFETs for EV traction inverters

This paper investigates the potential performance of high speed SiC cascode JFETs in EV traction inverters with high switching frequencies. Traction inverters implemented with SiC devices have shown improved energy conversion efficiency compared to IGBT based traction inverters however SiC MOSFETs suffer from unstable threshold voltage due to charge trapping at the SiC/SiO 2 (due to high density of traps). Since SiC cascode JFETs combine low voltage silicon MOSFETs (at the input) with high speed/high-power density SiC JFETs (at the output), cascode JFETs combine the electrical gate oxide reliability of silicon devices with the power density of SiC. This paper simulates an EV driving cycle using experimental power loss measurements (at different currents and temperatures) of commercially available 650V SiC cascode JFETs and SiC MOSFETs. The inverter has been simulated at 10, 25 and 50 kHz to investigate the impact of increased switching frequency on device losses. The model is fully electrothermal since conduction and switching losses have been measured at different junction temperatures and used as inputs to the model. The results show the potential of superior performance of the SiC cascode JFET in terms of power loss and junction temperature swings. Furthermore, since higher switching frequencies might be desirable in future high-speed traction motors, the fast switching and low loss performance of SiC Cascode JFETs becomes more attractive

Lifetime prediction for power converters

Renewable energy is developing rapidly and gaining more and more commercial viability. High reliability of the generation system is essential to maximize the output power. The power inverter is an important unit in this system and is believed to be one of the most unreliable parts. In the case of wind power generation, especially in off-shore wind, when the system reliability requirement is high, a technique to predict the inverter lifetime is invaluable as it would help the inverter designer optimize his design for minimal maintenance. Previous researchers studying inverter lifetime prediction, focus either at device level such as device fatigue damage models, or at system level which require experimental data for their selected device. This work presents a new method to estimate the inverter lifetime from a given mission profile within a reasonable simulation time. Such model can be used as a converter design tool or an on-line lifetime estimation tool after being configured to a real converter system. The key contribution of this work is to link the physics of the power devices to a large scale system simulation within a reasonable framework of time. With this technique, the system down time can be reduced and therefore more power can be generated. Also, the failure damage to the system is avoided which reduces the maintenance cost. A power cycling test is designed to gather the lifetime data of a selected IGBT module. Die-attach solder fatigue is found out to be the dominant failure mode of this IGBT module. The accuracy of widely accepted Miner’s rule, which accumulates damage linearly, is discussed and a nonlinear accumulation method is promoted to predict the lifetime of power inverters