System-on-Package Low-Power Telemetry and Signal Conditioning unit for Biomedical Applications

Recent advancements in healthcare monitoring equipments and wireless communication technologies have led to the integration of specialized medical technology with the pervasive wireless networks. Intensive research has been focused on the development of medical wireless networks (MWN) for telemedicine and smart home care services. Wireless technology also shows potential promises in surgical applications. Unlike conventional surgery, an expert surgeon can perform the surgery from a remote location using robot manipulators and monitor the status of the real surgery through wireless communication link. To provide this service each surgical tool must be facilitated with smart electronics to accrue data and transmit the data successfully to the monitoring unit through wireless network. To avoid unwieldy wires between the smart surgical tool and monitoring units and to reap the benefit of excellent features of wireless technology, each smart surgical tool must incorporate a low-power wireless transmitter. Low-power transmitter with high efficiency is essential for short range wireless communication. Unlike conventional transmitters used for cellular communication, injection-locked transmitter shows greater promises in short range wireless communication. The core block of an injection-locked transmitter is an injection-locked oscillator. Therefore, this research work is directed towards the development of a low-voltage low-power injection-locked oscillator which will facilitate the development of a low-power injection-locked transmitter for MWN applications. Structure of oscillator and types of injection are two crucial design criteria for low-power injection-locked oscillator design. Compared to other injection structures, body-level injection offers low-voltage and low-power operation. Again, conventional NMOS/PMOS-only cross-coupled LC oscillator can work with low supply voltage but the power consumption is relatively high. To overcome this problem, a self-cascode LC oscillator structure has been used which provides both low-voltage and low-power operation. Body terminal coupling is used with this structure to achieve injection-locking. Simulation results show that the self-cascode structure consumes much less power compared to that of the conventional structure for the same output swing while exhibiting better phase noise performance. Usage of PMOS devices and body bias control not only reduces the flicker noise and power consumption but also eliminates the requirements of expensive fabrication process for body terminal access

Millimeter-wave Communication and Radar Sensing — Opportunities, Challenges, and Solutions

With the development of communication and radar sensing technology, people are able to seek for a more convenient life and better experiences. The fifth generation (5G) mobile network provides high speed communication and internet services with a data rate up to several gigabit per second (Gbps). In addition, 5G offers great opportunities of emerging applications, for example, manufacture automation with the help of precise wireless sensing. For future communication and sensing systems, increasing capacity and accuracy is desired, which can be realized at millimeter-wave spectrum from 30 GHz to 300 GHz with several tens of GHz available bandwidth. Wavelength reduces at higher frequency, this implies more compact transceivers and antennas, and high sensing accuracy and imaging resolution. Challenges arise with these application opportunities when it comes to realizing prototype or demonstrators in practice. This thesis proposes some of the solutions addressing such challenges in a laboratory environment.High data rate millimeter-wave transmission experiments have been demonstrated with the help of advanced instrumentations. These demonstrations show the potential of transceiver chipsets. On the other hand, the real-time communication demonstrations are limited to either low modulation order signals or low symbol rate transmissions. The reason for that is the lack of commercially available high-speed analog-to-digital converters (ADCs); therefore, conventional digital synchronization methods are difficult to implement in real-time systems at very high data rates. In this thesis, two synchronous baseband receivers are proposed with carrier recovery subsystems which only require low-speed ADCs [A][B].Besides synchronization, high-frequency signal generation is also a challenge in millimeter-wave communications. The frequency divider is a critical component of a millimeter-wave frequency synthesizer. Having both wide locking range and high working frequencies is a challenge. In this thesis, a tunable delay gated ring oscillator topology is proposed for dual-mode operation and bandwidth extension [C]. Millimeter-wave radar offers advantages for high accuracy sensing. Traditional millimeter-wave radar with frequency-modulated continuous-wave (FMCW), or continuous-wave (CW), all have their disadvantages. Typically, the FMCW radar cannot share the spectrum with other FMCW radars.\ua0 With limited bandwidth, the number of FMCW radars that could coexist in the same area is limited. CW radars have a limited ambiguous distance of a wavelength. In this thesis, a phase-modulated radar with micrometer accuracy is presented [D]. It is applicable in a multi-radar scenario without occupying more bandwidth, and its ambiguous distance is also much larger than the CW radar. Orthogonal frequency-division multiplexing (OFDM) radar has similar properties. However, its traditional fast calculation method, fast Fourier transform (FFT), limits its measurement accuracy. In this thesis, an accuracy enhancement technique is introduced to increase the measurement accuracy up to the micrometer level [E]

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Design of low-voltage power efficient frequency dividers in folded MOS current mode logic

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter. Then an analytical strategy to optimize the divider in different design scenarios: maximum speed, minimum power-delay product (PDP) or minimum energy-delay product (EDP) is presented. The possibility to scale the bias currents through the divider stages without affecting the speed performance is also investigated. The proposed analytical approach allows to gain a deep insight into the circuit behavior and to comprehensively optimize the different design tradeoffs. The derived models and design guidelines are validated against transistor level simulations referring to a commercial 28nm FDSOI CMOS process. Different divide-by-8 circuits following different optimization strategies have been designed in the same 28nm CMOS technology showing the effectiveness of the proposed methodology

Techniques for Frequency Synthesizer-Based Transmitters.

Internet of Things (IoT) devices are poised to be the largest market for the semiconductor industry. At the heart of a wireless IoT module is the radio and integral to any radio is the transmitter. Transmitters with low power consumption and small area are crucial to the ubiquity of IoT devices. The fairly simple modulation schemes used in IoT systems makes frequency synthesizer-based (also known as PLL-based) transmitters an ideal candidate for these devices. Because of the reduced number of analog blocks and the simple architecture, PLL-based transmitters lend themselves nicely to the highly integrated, low voltage nanometer digital CMOS processes of today. This thesis outlines techniques that not only reduce the power consumption and area, but also significantly improve the performance of PLL-based transmitters.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113385/1/mammad_1.pd

A PLL frequency synthesizer and Gilbert cell multiplier for a 916 MHz ISM band transmitter realized in 0.5 [mu]m [i.e. micrometer] CMOS technology

This thesis is a study of the design of a 3rd order phase lock loop (PLL) and Gilbert cell multiplier to implement a 916MHz ISM band transmitter in 0.5μm CMOS technology. The transmitter is designed for implementing distributed biosensor systems for environmental monitoring. The transmitter is described from a system level with the discussion of design issues concerning system topology and communication signal requirements as related to project requirements. The PLL system is described as a negative feedback system and important design considerations are discussed. Each PLL and transmitter system component is analyzed and discussed. A prototyped double balanced Gilbert cell multiplier with a power gain of 8dB, -10dBm compression point, and dissipates 7.2mW of power is analyzed and presentedThe analysis and design of a prototyped current mode logic frequency divider with a fixed division factor of 256 is presented. The frequency divider dissipated 15mW of power for a -20dBm 916 MHz input signal with a maximum operating frequency of 1.8 GHz. An off-chip LC tank voltage controlled oscillator was prototyped with a tuning range of 120 MHz, dissipated 3.3mW, -15dBm single-ended output signal, and had a phase noise performance of -60dBc at a 10 kHz offset and -80dBc at 100 kHz offset is analyzed and presentedThe design and simulation issues of a digital phase frequency detector (PFD), charge pump, and loop filter is presented. The charge pump was designed to source or sink a 10 μA current for an output voltage to within 0.1 V of the power supply voltages. Results show that the final transmitter can be successfully implemented with the prototyped and simulated transmitter components

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam

Receiver Front-Ends in CMOS with Ultra-Low Power Consumption

Historically, research on radio communication has focused on improving range and data rate. In the last decade, however, there has been an increasing demand for low power and low cost radios that can provide connectivity with small devices around us. They should be able to offer basic connectivity with a power consumption low enough to function extended periods of time on a single battery charge, or even energy scavenged from the surroundings. This work is focused on the design of ultra-low power receiver front-ends intended for a receiver operating in the 2.4GHz ISM band, having an active power consumption of 1mW and chip area of 1mm². Low power consumption and small size make it hard to achieve good sensitivity and tolerance to interference. This thesis starts with an introduction to the overall receiver specifications, low power radio and radio standards, front-end and LO generation architectures and building blocks, followed by the four included papers. Paper I demonstrates an inductorless front-end operating at 915MHz, including a frequency divider for quadrature LO generation. An LO generator operating at 2.4GHz is shown in Paper II, enabling a front-end operating above 2GHz. Papers III and IV contain circuits with combined front-end and LO generator operating at or above the full 2.45GHz target frequency. They use VCO and frequency divider topologies that offer efficient operation and low quadrature error. An efficient passive-mixer design with improved suppression of interference, enables an LNA-less design in Paper IV capable of operating without a SAW-filter