A Low-Power Low-Voltage Bandgap Reference in CMOS

Bandgap reference plays a substantial role in integrated circuit. Traditionally, it provides a constant reference voltage of 1.2051/ for other blocks in the circuit while itself is independent of temperature and power supply. However, the development of CMOS technology has brought us into a new era of high integration and ultra-low power consumption. As the gate length scales down, it is crucial to build circuits that are able to work under a very low voltage power supply, for instance, lower than the bandgap voltage of 1.205V. Building bandgap circuits to generate the conven­ tional bandgap voltage under a low voltage power supply such as 1.2V or IV is no longer practical nor useful. Thus, bandgap references working under low-voltage and consuming low-power is becoming the trend of research and development nowadays. In this thesis work, the potential structure of a low-voltage low-power bandgap reference is proposed, which is based on extracting a current that is a fraction of the traditional bandgap voltage. All the necessary blocks are designed to achieve the high accuracy bandgap reference, including bandgap core circuit, op-amp, start-up circuit and output stage. As a result, the designed bandgap reference is able to work under 1.2V power supply and provides an output reference voltage of 584.7mV. It has a variation of only 244.38fiV for the temperature range of 0°C ~ 125°C and has a variation of only 1.1mV for a power supply range of 1.08V ~ 1.32V. The layout design for the bandgap reference structure is also done carefully at the late stage, with an area of 100fj,m x 85¡xm

500mV low-voltage operational amplifier design

With the dramatic increase in the number of transistors on a chip and the increasing needs for battery-powered applications, low-voltage circuit design techniques have been widely studied in recent year. However, these low supply voltage research efforts have been focused mainly on digital circuits, especially on high density memory circuits. Reported success in achieved high performance low voltage operation in analog circuits lags far behind. Recent results have been presented on CMOS low-voltage operational amplifiers, where the supply voltage has been reduced to less than 2.5V in which the complementary input stages were used to keep the gm constant [SI95] [HL85]. Recently, the floating gate MOS transistor has attracted considerable interest as a nonvolatile analog storage device and as a precision analog trim element because it has threshold voltage programming ability [YU93] [RC95].;The particular focus of this work is on implementing very low voltage analog and mixed-signal integrated circuit in a standard CMOS process. As a proof-of-concept vehicle, this work concentrates on the design of very low voltage operational amplifiers in standard CMOS processes. By connecting a DC reference voltage source in series with the gate of all MOS transistors, the equivalent threshold voltage of all transistors can be electrically lowered. This technique makes it possible to decrease the power supply voltage. The DC reference voltage sources are realized by using a switched capacitor charged periodically and switched between the actual circuit and a reference precharge circuit. By extracting the reference voltage source directly from the threshold voltage itself, the threshold voltage variations due to the process and temperature variations can be compensated, since large threshold variations are intolerable for very low threshold voltage applications.;In a proof-of-concept two-stage operational amplifier designed to operate with a single 5OOmV power supply in a standard 2[Mu] process, the tail current is kept the same as in a 3.3V design, thus the key performance parameters are expected to be maintained at reasonable values. The dramatic decrease of the power supply possible with this approach is paralleled with a corresponding reduction in the power dissipation. Simulation results of this 5OOmV operational amplifier show a 7OdB DC gain, 7.8MHz unity gain bandwidth and a 650 phase margin. Power dissipation is reduced by more than 90% from that of the corresponding 3.3V design. Although the specific implementation is focused on the implementation of an operational amplifier with comparable performance parameters to those with larger supply voltage, the dominant applications of this technique are for designing a variety of analog and mixed-signal systems that operate at very low voltages and with low power dissipation

128 mA CMOS LDO with 108 db PSRR at 2.4 MHz frequency

A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented in this paper. Large 1µF off-chip load capacitor is used to achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC. The characteristic is achieved by implementing MOSFET transistors operate in weak and strong inversions. The LDO is designed using 0.18µm CMOS technology and achieves a constant 1.8V output voltage for input voltages from 3.2V to 5V and load current up to a 128mA at temperature between -40°C to 125°C. The proposed LDO is targeted for RF application which has stringent requirement on noise rejection over a broad range of frequency

A Radiation hard bandgap reference circuit in a standard 0.13um CMOS Technology

With ongoing CMOS evolution, the gate-oxide thickness steadily decreases, resulting in an increased radiation tolerance of MOS transistors. Combined with special layout techniques, this yields circuits with a high inherent robustness against X-rays and other ionizing radiation. In bandgap voltage references, the dominant radiation-susceptibility is then no longer associated with the MOS transistors, but is dominated by the diodes. This paper gives an analysis of radiation effects in both MOSdevices and diodes and presents a solution to realize a radiation-hard voltage reference circuit in a standard CMOS technology. A demonstrator circuit was implemented in a standard 0.13 m CMOS technology. Measurements show correct operation with supply voltages in the range from 1.4 V down to 0.85 V, a reference voltage of 405 mV 7.5 mV ( = 6mVchip-to-chip statistical spread), and a reference voltage shift of only 1.5 mV (around 0.8%) under irradiation up to 44 Mrad (Si)

Output-capacitorless low-dropout regulator for power management applications

This article aims to present the design of a 4.5-V, 450-mA low drop-out (LDO) voltage linear regulator based on a two-stage cascoded operational transconductance amplifier (OTA) as error amplifier. The aforementioned two-stage OTA is designed with cascoded current mirroring technique to boost up the output impedance. The proposed OTA has a DC gain of 101 dB under no load condition. The designed reference voltage included in the LDO regulator is provided by a band gap reference with the temperature coefficient (T¿) of 0.025 mV/ºC. The proposed LDO regulator has a maximum drop-out voltage of 0.5 V @ 450 mA of load current, and has the worst case power supply rejection ratio (PSRR) of [54.5 dB, 34.3 dB] @ [100 Hz, 10 kHz] in full load condition. All the proposed circuits are designed using a 0.35 µm CMOS technology. The design is checked in order to corroborate its performance for wide range of input voltage, founding that the circuit design works fine meeting all the initial specification requirements.Postprint (published version

Design of an output-capacitorless low-dropout regulator for power management applications

This article aims to present the design of a 4.5-V, 450-mA low drop-out (LDO) voltage linear regulator based on a twostage cascoded operational transconductance amplifier (OTA) as error amplifier. The aforementioned two-stage OTA is designed with cascoded current mirroring technique to boost up the output impedance. The proposed OTA has a DC gain of 101 dB under no load condition. The designed reference voltage included in the LDO regulator is provided by a band gap reference with the temperature coefficient (T¿) of 0.025 mV/ºC. The proposed LDO regulator has a maximum drop-out voltage of 0.5 V @ 450 mA of load current, and has the worst case power supply rejection ratio (PSRR) of [54.5 dB, 34.3 dB] @ [100 Hz, 10 kHz] in full load condition. All the proposed circuits are designed using a 0.35 µm CMOS technology. The design is checked in order to corroborate its performance for wide range of input voltage, founding that the circuit design works fine meeting all the initial specification requirements.Postprint (published version

Design of a single-chip pH sensor using a conventional 0.6-μm CMOS process

A pH sensor fabricated on a single chip by an unmodified, commercial 0.6-/spl μm CMOS process is presented. The sensor comprises a circuit for making differential measurements between an ion-sensitive field-effect transistor (ISFET) and a reference FET (REFET). The ISFET has a floating-gate structure and uses the silicon nitride passivation layer as a pH-sensitive insulator. As fabricated, it has a large threshold voltage that is postulated to be caused by a trapped charge on the floating gate. Ultraviolet radiation and bulk-substrate biasing is used to permanently modify the threshold voltage so that the ISFET can be used in a battery-operated circuit. A novel post-processing method using a single layer of photoresist is used to define the sensing areas and to provide robust encapsulation for the chip. The complete circuit, operating from a single 3-V supply, provides an output voltage proportional to pH and can be powered down when not required

A Fully Differential CMOS Potentiostat

A CMOS potentiostat for chemical sensing in a noisy environment is presented. The potentiostat measures bidirectional electrochemical redox currents proportional to the concentration of a chemical down to pico-ampere range. The fully differential architecture with differential recording electrodes suppresses the common mode interference. A 200μm×200μm prototype was fabricated in a standard 0.35μm standard CMOS technology and yields a 70dB dynamic range. The in-channel analog-to-digital converter (ADC) performs 16-bit current-tofrequency quantization. The integrated potentiostat functionality is validated in electrical and electrochemical experiments

A system-on-chip digital pH meter for use in a wireless diagnostic capsule

This paper describes the design and implementation of a system-on-chip digital pH meter, for use in a wireless capsule application. The system is organized around an 8-bit microcontroller, designed to be functionally identical to the Motorola 6805. The analog subsystem contains a floating-electrode ISFET, which is fully compatible with a commercial CMOS process. On-chip programmable voltage references and multiplexors permit flexibility with the minimum of external connections. The chip is designed in a modular fashion to facilitate verification and component re-use. The single-chip pH meter can be directly connected to a personal computer, and gives a response of 37 bits/pH, within an operating range of 7 pH units

A CMOS analog continuous-time delay line with adaptive delay-time control

A CMOS analog continuous-time delay line composed of cascaded first-order current-domain all-pass sections is discussed. Each all-pass section consists of CMOS transistors and a single capacitor. The operation is based on the square-law characteristic of an MOS transistor in saturation. The delay time per section can either be controlled by an external voltage or locked to an external reference frequency by means of a control system which features a large capture range. Experimental verification has been performed on two setups: an integrated cascade of 26 identical all-pass sections and a frequency-locking system breadboard built around two identical on-chip all-pass section