Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 173-176).Copper metallization has emerged as the leading interconnect technology for deep sub-micron features, where electroplating and chemical mechanical polish (CMP) processes have a vital role in the fabrication of integrated circuits. The processes both suffer from a similar problem: the copper electroplated profiles and the polished surface exhibit pattern dependent topography. In this thesis, a methodology for the characterization and modeling of pattern dependent problems in copper interconnect topography is developed. For the electroplating process, the methodology consists of test structure and mask design to examine feature scale copper step height and the height of copper array regions as a function of underlying layout parameters. Semi-empirical response surface models are then generated with model parameters extracted from conventional and superfill plating processes. Once the models are calibrated, layout parameters including pattern density, line width distributions, and line length are extracted for each cell in a 40 gm by 40 tm discretization of any random chip layout. Then, a chip-scale prediction is achieved by simulating generalized average heights for each grid cell across the entire chip. The prediction result shows root mean square errors of less than 1000 A for array height and around 500 A for step height. This methodology provides the first known chip-scale prediction of electroplated topography. For pattern dependencies in copper CMP, this thesis focuses on the development of test structures and masks (including multi-level structures) to identify key pattern effects in both single-level and multi-level polishing.(cont.) Especially for the multi-level studies, electrical test structures and measurements in addition to surface profile scans are seen to be important in accurately determining thickness variations. The developed test vehicle and characterization of copper dishing and oxide erosion serve as a basis for further pattern dependent model development. Finally, integration of electroplating and CMP chip-scale models is illustrated; the simulated step and array heights as well as topography pattern density are used as an input for the initial starting topography for CMP simulation of subsequent polishing profile evolution.by Tae Hong Park.Ph.D

Modeling of pattern dependencies in the fabrication of multilevel copper metallization

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.Includes bibliographical references (p. 295-303).Multilevel copper metallization for Ultra-Large-Scale-Integrated (ULSI) circuits is a critical technology needed to meet performance requirements for advanced interconnect technologies with sub-micron dimensions. It is well known that multilevel topography resulting from pattern dependencies in various processes, especially copper Electrochemical Deposition (ECD) and Chemical-Mechanical Planarization (CMP), is a major problem in interconnects. An integrated pattern dependent chip-scale model for multilevel copper metallization is contributed to help understand and meet dishing and erosion requirements, to optimize the combined plating and polishing process to achieve minimal environmental impact, higher yield and performance, and to enable optimization of layout and dummy fill designs. First, a physics-based chip-scale copper ECD model is developed. By considering copper ion depletion effects, and surface additive adsorption and desorption, the plating model is able to predict the initial topography for subsequent CMP modeling with sufficient accuracy and computational efficiency. Second, a compatible chip-scale CMP modeling is developed.(cont.) The CMP model integrates contact wear and density-step-height approaches, so that a consistent and coherent chip-scale model framework can be used for copper bulk polishing, copper over-polishing, and barrier layer polishing stages. A variant of this CMP model is developed which explicitly considers the pad topography properties. Finally, ECD and CMP parts are combined into an integrated model applicable to single level and multilevel metallization cases. The integrated multilevel copper metallization model is applied to the co-optimization of the plating and CMP processes. An alternative in-pattern (rather than between-pattern) dummy fill strategy is proposed. The integrated ECD/CMP model is applied to the optimization of the in-pattern fill, to achieve improved ECD uniformity and final post-CMP topography.by Hong Cai.Ph.D

Chip-scale modeling of pattern dependencies in copper chemical mechanical polishing processes

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 229-232).Chemical mechanical polishing (CMP) has become a necessary processing step in the fabrication of copper interconnects. Copper CMP is recognized to suffer from pattern dependent problems such as dishing and erosion, which cause increased line resistance and non-uniformity within the die. The non-uniformity on one metal level can lead to cumulative non-uniformity on higher metal levels, leading to potential integration and manufacturing problems. Predictive pattern dependent models of copper CMP processes are therefore highly desirable for predicting dishing and erosion on random layouts, assessing the effectiveness of dummy fills in minimizing within-die non-uniformity, aiding in the generation of smart interconnect design rules, and identifying potential bulk copper clearing problems in multi-level metallization designs. In this thesis, the first predictive semi-physical chip-scale pattern dependent model for copper CMP processes is developed. A comprehensive model calibration methodology for any multi-step copper CMP process is also developed. The model takes into account the initial long range electroplated topography, the effective pattern density, and the initial local step heights within the arrays. The model also accounts for the temporal evolution of the bulk copper thickness during CMP, the temporal evolution of dishing and erosion, and the layout dependencies of dishing and erosion. A three step conventional copper CMP process experiment and a single step abrasive-free copper CMP process experiment are performed to test the accuracy of the model and the calibration methodology.(cont.) The results show that the model predicts the trends in the experimental data accurately, and fits the data to within acceptable errors. The model and the calibration methodology are integrated with an empirical pattern dependent electroplating model and calibration methodology, to form a chip-scale copper electroplating and CMP simulator. Once the models that form the simulator are calibrated for a given copper CMP process, and a given copper electroplating process, the simulator can be used to: (1) predict dishing and erosion across an entire chip, for a random layout; (2) assess the effectiveness of dummy fills in minimizing within-die non-uniformity; (3) identify bulk copper clearing problems in multi-level metallization designs; and (4) aid in the generation of smart interconnect design rules. Preliminary experimental results show that the simulator predicts dishing and erosion across an entire chip reasonably well, for a random layout.by Tamba E. Gbondo-Tugbawa.Ph.D

Electrophoretic deposition of ferrite

The ability to integrate a material with a high permeability on chip, allows for magnetically coupled circuits and structures to be designed and incorporated along side CMOS circuitry. Devices ranging from A.C. transformers to magnetically driven MEMS structures can be designed and fabricated. Desirable characteristics of magnetic cores for integrated inductors and transformers are first high saturation flux in order to obtain high saturation current; high permeability to obtain high inductance; high resistivity to reduce eddy current loss at high frequencies and compatible deposition and patterning processes. High frequency magnetic materials are oxide based ceramics and are therefore difficult to evaporate, sputter, plate and selectively etched. ElectroPhoretic Deposition (EPD) is a method where insulating particles are imparted charge in a suspension and are made to deposit on an electrode by applying electric field. EPD has been extensively employed in depositing oxide based phosphors for display applications. In this study, ferrite particles have been prepared by grinding sintered toroids and deposited by EPD. The electrophoretic solution bath is composed of isopropyl alcohol with traces of Mg(N03)2 and La(N03)3 salts. Glycerol is added to the solution bath as a surfactant to promote increased substrate adhesion. The dissociation of magnesium nitrate in the solution bath charges the ferrite particles. An electric field of ~ 50-160 V/cm is applied with negative terminal connected to the wafer to be plated and aluminum electrode is used as the anode. The deposition process is found to be self limiting with the initial high elerophoretic current declining to 10% of its value in 10 minutes. The deposition rate and zeta potential measurements indicate a high particle velocity on the order 5.7x10-3 cm/s with an electric field of 160V/cm generated across the 2 cm electrode spacing. Pattern filling and conformal coverage in copper damascene planar microinductors has been investigated. A method to extracted permeability from S11 impedance analysis has been employed. It has been found that grinding process deteriorates magnetic response. With recent advances in magnetic particle technology for high frequency materials, these results enable unique hard and soft powder ferrite material to be selectively deposited in wide variety of CMOS and MEM’s based applications

Modeling Dielectric Erosion in Multi-Step Copper Chemical-Mechanical Polishing

A formidable challenge in the present multi-step Cu CMP process, employed in the ultra-large-scale integration (ULSI) technology, is the control of wafer surface non-uniformity, which primarily is due to dielectric erosion and Cu dishing. In contrast with the earlier experimental and semi-theoretical investigations, a systematic way of characterizing and modeling dielectric erosion in both single- and multi-step Cu CMP processes is presented in this paper. Wafer- and die-level erosion are defined, and the plausible causes of erosion at each level are identified in terms of several geometric and physical parameters. Experimental and analytical means of determining the model parameters are also outlined. The local pressure distribution is estimated at each polishing stage based on the evolving pattern geometry and pad deformation. The single-step model is adapted for the multi-step polishing process, with multiple sets of slurry selectivities, applied pressure, and relative velocity in each step. Finally, the effect of slurry-switching point on erosion was investigated for minimizing dielectric erosion in the multi-step Cu CMP. Based on the developed multi-step erosion model, the physical significance of each model parameter on dielectric erosion is determined, and the optimal polishing practices for minimizing erosion in both multi-step and single-step polishing are suggested.Singapore-MIT Alliance (SMA

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis work aims at fabricating through-silicon vias (TSVs) on diced processor chips, and later bonding them into a 3D-stacked chip. How to handle and process delicate processor chips with high alignment precision is a key issue. The TSV process to be developed also needs to adapt to this constraint. Four TSV processes have been studied. Among them, the ring-trench TSV process demonstrates the feasibility of fabricating TSVs with the prevailing dimensions, and the whole-through TSV process achieves the first dummy chip post-processed with TSVs in EPFL although the dimension is rather large to keep a reasonable aspect ratio (AR). Four self-alignment (SA) techniques have been investigated, among which the gravitational SA and the hydrophobic SA are found to be quite promising. Using gravitational SA, we come to the conclusion that cavities in silicon carrier wafer with a profile angle of 60° can align the chips with less than 20 µm inaccuracies. The alignment precision can be improved after adopting more advanced dicing tools instead of using the traditional dicing saws and larger cavity profile angle. Such inaccuracy will be sufficient to align the relatively large TSVs for general products such as 3D image sensors. By fabricating bottom TSVs in the carrier wafer, a 3D silicon interposer idea has been proposed to stack another chip, e.g. a processor chip, on the other side of the carrier wafer. But stacking microprocessor chips fabricated with TSVs will require higher alignment precision. A hydrophobic SA technique using the surface tension force generated by the water-to-air interfaces around the pads can greatly reduce the alignment inaccuracy to less than 1 µm. This low-cost and high throughput SA procedure is processed in air, fully-compatible with current fabrication technologies, and highly stable and repeatable. We present a theoretical meniscus model to predict SA results and to provide the design rules. This technique is quite promising for advanced 3D applications involving logic and heterogeneous stacking. As TSVs' dimensions in the chip-level 3D integration are constrained by the chip-level processes, such as bonding, the smallest TSVs might still be about 5 µm. Thus, the area occupied by the TSVs cannot be neglected. Fortunately, TSVs can withstand very high bandwidths, meaning that data can be serialized and transmitted using less numbers of TSVs. With 20 µm TSVs, the 2-Gb/s 8:1 serial link implemented saves 75% of the area of its 8-bit parallel counterpart. The quasi-serial link proposed can effectively balance the inter-layer bandwidth and the serial links' area consumption. The area model of the serial or quasi-serial links working under higher frequencies provides some guidelines to choose the proper serial link design, and it also predicts that when TSV diameter shrinks to 5 µm, it will be difficult to keep this area benefit if without some novel circuit design techniques. As the serial links can be implemented with less area, the bandwidth per unit area is increased. Two scenarios are studied, single-port memory access and multi-port memory access. The expanded inter-layer bandwidth by serialization does not improve the system performance because of the bus-bottleneck problem. In the latter scenario, the inter-layer ultra-wide bandwidth can be exploited as each memory bank can be accessed randomly through the NoC. Thus further widening the inter-layer bandwidth through serialization, the system performance will be improved

Nanoparticle Engineering for Chemical-Mechanical Planarization

Increasing reliance on electronic devices demands products with high performance and efficiency. Such devices can be realized through the advent of nanoparticle technology. This book explains the physicochemical properties of nanoparticles according to each step in the chemical mechanical planarization (CMP) process, including dielectric CMP, shallow trend isolation CMP, metal CMP, poly isolation CMP, and noble metal CMP. The authors provide a detailed guide to nanoparticle engineering of novel CMP slurry for next-generation nanoscale devices below the 60nm design rule. This comprehensive text also presents design techniques using polymeric additives to improve CMP performance

Development and testing of a micromachined probe card.

This thesis is concerned with the design, fabrication and testing of micro scale probes. The probes were designed to act as temporary electrical connections to allow wafer level testing of integrated circuits. The work initially focused on the creation of free standing nickel cantilevers, angled up from the substrate with probe tips at the free end. These were fabricated using a novel method, combining pseudo grey scale lithography and thick photoresist sacrificial layers. Detailed analysis of the fabrication method, in particular the resist processing and lithography was undertaken and the limitations of the method explored.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Fabrication of an Atom Chip for Rydberg Atom-Metal Surface Interaction Studies

This thesis outlines the fabrication of two atom chips for the study of interactions between ⁸⁷Rb Rydberg atoms and a Au surface. Atom chips yield tightly confined, cold samples of an atomic species by generating magnetic fields with high gradients using microfabricated current-carrying wires. These ground state atoms may in turn be excited to Rydberg states. The trapping wires of Chip 1 are fabricated using thermally evaporated Cr/Au and patterned using lift-off photolithography. Chip 2 uses a Ti/Pd/Au tri-layer, instead of Cr/Au, to minimize interdiffusion. The chip has a thermally evaporated Au surface layer for Rydberg atom-surface interactions, which is separated from the underlying trapping wires by a planarizing polyimide dielectric. The polyimide was patterned using reactive ion etching. Special attention was paid to the edge roughness and electrical properties of the trapping wires, the planarization of the polyimide, and the grain structure of the Au surface