1,625 research outputs found

    A Survey Addressing on High Performance On-Chip VLSI Interconnect

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    With the rapid increase in transmission speeds of communication systems, the demand for very high-speed lowpower VLSI circuits is on the rise. Although the performance of CMOS technologies improves notably with scaling, conventional CMOS circuits cannot simultaneously satisfy the speed and power requirements of these applications. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, power and delay optimization and also comparative analysis of various techniques for high speed design have been discussed

    ์ฐจ์„ธ๋Œ€ ์ž๋™์ฐจ์šฉ ์นด๋ฉ”๋ผ ๋ฐ์ดํ„ฐ ํ†ต์‹ ์„ ์œ„ํ•œ ๋น„๋Œ€์นญ ๋™์‹œ ์–‘๋ฐฉํ–ฅ ์†ก์ˆ˜์‹ ๊ธฐ์˜ ์„ค๊ณ„

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    ํ•™์œ„๋…ผ๋ฌธ(๋ฐ•์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2022.2. ์ •๋•๊ท .๋ณธ ํ•™์œ„ ๋…ผ๋ฌธ์—์„œ๋Š” ์ฐจ์„ธ๋Œ€ ์ž๋™์ฐจ์šฉ ์นด๋ฉ”๋ผ ๋งํฌ๋ฅผ ์œ„ํ•ด ๋†’์€ ์†๋„์˜ 4๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ์‹ ํ˜ธ์™€ ๋‚ฎ์€ ์†๋„์˜ 2๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ์‹ ํ˜ธ๋ฅผ ํ†ต์‹ ํ•˜๋Š” ๋น„๋Œ€์นญ ๋™์‹œ ์–‘๋ฐฉํ–ฅ ์†ก์ˆ˜์‹ ๊ธฐ์˜ ์„ค๊ณ„ ๊ธฐ์ˆ ์— ๋Œ€ํ•ด ์ œ์•ˆํ•˜๊ณ  ๊ฒ€์ฆ๋˜์—ˆ๋‹ค. ์ฒซ๋ฒˆ์งธ ํ”„๋กœํ† ํƒ€์ž… ์„ค๊ณ„์—์„œ๋Š”, 10B6Q ์ง๋ฅ˜ ๋ฐธ๋Ÿฐ์Šค ์ฝ”๋“œ๋ฅผ ํƒ‘์žฌํ•œ 4๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ์†ก์‹ ๊ธฐ์™€ ๊ณ ์ •๋œ ๋ฐ์ดํ„ฐ์™€ ์ฐธ์กฐ ๋ ˆ๋ฒจ์„ ๊ฐ€์ง€๋Š” 4๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ์ ์‘ํ˜• ์ˆ˜์‹ ๊ธฐ์— ๋Œ€ํ•œ ๋‚ด์šฉ์ด ๊ธฐ์ˆ ๋˜์—ˆ๋‹ค. 4๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ์†ก์‹ ๊ธฐ์—์„œ๋Š” ๊ต๋ฅ˜ ์—ฐ๊ฒฐ ๋งํฌ ์‹œ์Šคํ…œ์— ๋Œ€์‘ํ•˜๊ธฐ ์œ„ํ•œ ๋ฉด์  ๋ฐ ์ „๋ ฅ ํšจ์œจ์„ฑ์ด ์ข‹์€ 10B6Q ์ฝ”๋“œ๊ฐ€ ์ œ์•ˆ๋˜์—ˆ๋‹ค. ์ด ์ฝ”๋“œ๋Š” ์ง๋ฅ˜ ๋ฐธ๋Ÿฐ์Šค๋ฅผ ๋งž์ถ”๊ณ  ์—ฐ์†์ ์œผ๋กœ ๊ฐ™์€ ์‹ฌ๋ณผ์„ ๊ฐ€์ง€๋Š” ๊ธธ์ด๋ฅผ 6๊ฐœ๋กœ ์ œํ•œ ์‹œํ‚จ๋‹ค. ๋น„๋ก ์—ฌ๊ธฐ์„œ๋Š” ์ž…๋ ฅ ๋ฐ์ดํ„ฐ ๊ธธ์ด 10๋น„ํŠธ๋ฅผ ์‚ฌ์šฉํ•˜์˜€์ง€๋งŒ, ์ œ์•ˆ๋œ ๊ธฐ์ˆ ์€ ์นด๋ฉ”๋ผ์˜ ๋‹ค์–‘ํ•œ ๋ฐ์ดํ„ฐ ํƒ€์ž…์— ๋Œ€์‘ํ•  ์ˆ˜ ์žˆ๋„๋ก ์ž…๋ ฅ ๋ฐ์ดํ„ฐ ๊ธธ์ด์— ๋Œ€ํ•œ ํ™•์žฅ์„ฑ์„ ๊ฐ€์ง„๋‹ค. ๋ฐ˜๋ฉด, 4๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ์ ์‘ํ˜• ์ˆ˜์‹ ๊ธฐ์—์„œ๋Š”, ์ƒ˜ํ”Œ๋Ÿฌ์˜ ์˜ต์…‹์„ ์ตœ์ ์œผ๋กœ ์ œ๊ฑฐํ•˜์—ฌ ๋” ๋‚ฎ์€ ๋น„ํŠธ์—๋Ÿฌ์œจ์„ ์–ป๊ธฐ ์œ„ํ•ด์„œ, ๊ธฐ์กด์˜ ๋ฐ์ดํ„ฐ ๋ฐ ์ฐธ์กฐ ๋ ˆ๋ฒจ์„ ์กฐ์ ˆํ•˜๋Š” ๋Œ€์‹ , ์ด ๋ ˆ๋ฒจ๋“ค์€ ๊ณ ์ •์‹œํ‚ค๊ณ  ๊ฐ€๋ณ€ ๊ฒŒ์ธ ์ฆํญ๊ธฐ๋ฅผ ์ ์‘ํ˜•์œผ๋กœ ์กฐ์ ˆํ•˜๋„๋ก ํ•˜์˜€๋‹ค. ์ƒ๊ธฐ 10B6Q ์ฝ”๋“œ ๋ฐ ๊ณ ์ • ๋ฐ์ดํ„ฐ ๋ฐ ์ฐธ์กฐ๋ ˆ๋ฒจ ๊ธฐ์ˆ ์„ ๊ฐ€์ง„ ํ”„๋กœํ† ํƒ€์ž… ์นฉ๋“ค์€ 40 ๋‚˜๋…ธ๋ฏธํ„ฐ ์ƒํ˜ธ๋ณด์™„ํ˜• ๋ฉ”ํƒˆ ์‚ฐํ™” ๋ฐ˜๋„์ฒด ๊ณต์ •์œผ๋กœ ์ œ์ž‘๋˜์—ˆ๊ณ  ์นฉ ์˜จ ๋ณด๋“œ ํ˜•ํƒœ๋กœ ํ‰๊ฐ€๋˜์—ˆ๋‹ค. 10B6Q ์ฝ”๋“œ๋Š” ํ•ฉ์„ฑ ๊ฒŒ์ดํŠธ ์ˆซ์ž๋Š” 645๊ฐœ์™€ ํ•จ๊ป˜ ๋‹จ 0.0009 mm2 ์˜ ๋ฉด์  ๋งŒ์„ ์ฐจ์ง€ํ•œ๋‹ค. ๋˜ํ•œ, 667 MHz ๋™์ž‘ ์ฃผํŒŒ์ˆ˜์—์„œ ๋‹จ 0.23 mW ์˜ ์ „๋ ฅ์„ ์†Œ๋ชจํ•œ๋‹ค. 10B6Q ์ฝ”๋“œ๋ฅผ ํƒ‘์žฌํ•œ ์†ก์‹ ๊ธฐ์—์„œ 8-Gb/s 4๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ์‹ ํ˜ธ๋ฅผ ๊ณ ์ • ๋ฐ์ดํ„ฐ ๋ฐ ์ฐธ์กฐ ๋ ˆ๋ฒจ์„ ๊ฐ€์ง€๋Š” ์ ์‘ํ˜• ์ˆ˜์‹ ๊ธฐ๋กœ 12-m ์ผ€์ด๋ธ” (22-dB ์ฑ„๋„ ๋กœ์Šค) ์„ ํ†ตํ•ด์„œ ๋ณด๋‚ธ ๊ฒฐ๊ณผ ์ตœ์†Œ ๋น„ํŠธ ์—๋Ÿฌ์œจ 108 ์„ ๋‹ฌ์„ฑํ•˜์˜€๊ณ , ๋น„ํŠธ ์—๋Ÿฌ์œจ 105 ์—์„œ๋Š” ์•„์ด ๋งˆ์ง„์ด 0.15 UI x 50 mV ๋ณด๋‹ค ํฌ๊ฒŒ ์ธก์ •๋˜์—ˆ๋‹ค. ์†ก์ˆ˜์‹ ๊ธฐ๋ฅผ ํ•ฉ์นœ ์ „๋ ฅ ์†Œ๋ชจ๋Š” 65.2 mW (PLL ์ œ์™ธ) ์ด๊ณ , ์„ฑ๊ณผ์˜ ๋Œ€ํ‘œ์ˆ˜์น˜๋Š” 0.37 pJ/b/dB ๋ฅผ ๋ณด์—ฌ์ฃผ์—ˆ๋‹ค. ์ฒซ๋ฒˆ์งธ ํ”„๋กœํ† ํƒ€์ž… ์„ค๊ณ„์„ ํฌํ•จํ•˜์—ฌ ๊ฐœ์„ ๋œ ๋‘๋ฒˆ์งธ ํ”„๋กœํ† ํƒ€์ž… ์„ค๊ณ„์—์„œ๋Š”, 12-Gb/s 4๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ์ •๋ฐฉํ–ฅ ์ฑ„๋„ ์‹ ํ˜ธ์™€ 125-Mb/s 2๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ์—ญ๋ฐฉํ–ฅ ์ฑ„๋„ ์‹ ํ˜ธ๋ฅผ ํƒ‘์žฌํ•œ ๋น„๋Œ€์นญ ๋™์‹œ ์–‘๋ฐฉํ–ฅ ์†ก์ˆ˜์‹ ๊ธฐ์— ๋Œ€ํ•ด ๊ธฐ์ˆ ๋˜๊ณ  ๊ฒ€์ฆ๋˜์—ˆ๋‹ค. ์ œ์•ˆ๋œ ๋„“์€ ์„ ํ˜• ๋ฒ”์œ„๋ฅผ ๊ฐ€์ง€๋Š” ํ•˜์ด๋ธŒ๋ฆฌ๋“œ๋Š” gmC ์ €๋Œ€์—ญ ํ†ต๊ณผ ํ•„ํ„ฐ์™€ ์—์ฝ” ์ œ๊ฑฐ๊ธฐ์™€ ํ•จ๊ป˜ ์•„์›ƒ๋ฐ”์šด๋“œ ์‹ ํ˜ธ๋ฅผ 24 dB ์ด์ƒ ํšจ์œจ์ ์œผ๋กœ ๊ฐ์†Œ์‹œ์ผฐ๋‹ค. ๋˜ํ•œ, ๋„“์€ ์„ ํ˜• ๋ฒ”์œ„๋ฅผ ๊ฐ€์ง€๋Š” ํ•˜์ด๋ธŒ๋ฆฌ๋“œ์™€ ํ•จ๊ป˜ ๊ฒŒ์ธ ๊ฐ์†Œ๊ธฐ๋ฅผ ํ˜•์„ฑํ•˜๊ฒŒ ๋˜๋Š” ์„ ํ˜• ๋ฒ”์œ„ ์ฆํญ๊ธฐ๋ฅผ ํ†ตํ•ด 4๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ์‹ ํ˜ธ์˜ ์„ ํ˜•์„ฑ๊ณผ ์ง„ํญ์˜ ํŠธ๋ ˆ์ด๋“œ ์˜คํ”„ ๊ด€๊ณ„๋ฅผ ๊นจ๋Š” ๊ฒƒ์ด ๊ฐ€๋Šฅํ•˜์˜€๋‹ค. ๋™์‹œ ์–‘๋ฐฉํ–ฅ ์†ก์ˆ˜์‹ ๊ธฐ ์นฉ์€ 40 ๋‚˜๋…ธ๋ฏธํ„ฐ ์ƒํ˜ธ๋ณด์™„ํ˜• ๋ฉ”ํƒˆ ์‚ฐํ™” ๋ฐ˜๋„์ฒด ๊ณต์ •์œผ๋กœ ์ œ์ž‘๋˜์—ˆ๋‹ค. ์ƒ๊ธฐ ์„ค๊ณ„ ๊ธฐ์ˆ ๋“ค์„ ์ด์šฉํ•˜์—ฌ, 4๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ๋ฐ 2๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ์†ก์ˆ˜์‹ ๊ธฐ ๋ชจ๋‘ 5m ์ฑ„๋„ (์ฑ„๋„ ๋กœ์Šค 15.9 dB) ์—์„œ 1E-12 ๋ณด๋‹ค ๋‚ฎ์€ ๋น„ํŠธ ์—๋Ÿฌ์œจ์„ ๋‹ฌ์„ฑํ•˜์˜€๊ณ , ์ด 78.4 mW ์˜ ์ „๋ ฅ ์†Œ๋ชจ๋ฅผ ๊ธฐ๋กํ•˜์˜€๋‹ค. ์ข…ํ•ฉ์ ์ธ ์†ก์ˆ˜์‹ ๊ธฐ๋Š” ์„ฑ๊ณผ ๋Œ€ํ‘œ์ง€ํ‘œ๋กœ 0.41 pJ/b/dB ์™€ ํ•จ๊ป˜ ๋™์‹œ ์–‘๋ฐฉํ–ฅ ํ†ต์‹  ์•„๋ž˜์—์„œ 4๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ์‹ ํ˜ธ ๋ฐ 2๋ ˆ๋ฒจ ํŽ„์Šค ์ง„ํญ ๋ณ€์กฐ ์‹ ํ˜ธ ๊ฐ๊ฐ์—์„œ ์•„์ด ๋งˆ์ง„ 0.15 UI ์™€ 0.57 UI ๋ฅผ ๋‹ฌ์„ฑํ•˜์˜€๋‹ค. ์ด ์ˆ˜์น˜๋Š” ์„ฑ๊ณผ ๋Œ€ํ‘œ์ง€ํ‘œ 0.5 ์ดํ•˜๋ฅผ ๊ฐ€์ง€๋Š” ๊ธฐ์กด ๋™์‹œ ์–‘๋ฐฉํ–ฅ ์†ก์ˆ˜์‹ ๊ธฐ์™€์˜ ๋น„๊ต์—์„œ ์ตœ๊ณ ์˜ ์•„์ด ๋งˆ์ง„์„ ๊ธฐ๋กํ•˜์˜€๋‹ค.In this dissertation, design techniques of a highly asymmetric simultaneous bidirectional (SB) transceivers with high-speed PAM-4 and low-speed PAM-2 signals are proposed and demonstrated for the next-generation automotive camera link. In a first prototype design, a PAM-4 transmitter with 10B6Q DC balance code and a PAM-4 adaptive receiver with fixed data and threshold levels (dtLevs) are presented. In PAM-4 transmitter, an area- and power-efficient 10B6Q code for an AC coupled link system that guarantees DC balance and limited run length of six is proposed. Although the input data width of 10 bits is used here, the proposed scheme has an extensibility for the input data width to cover various data types of the camera. On the other hand, in the PAM-4 adaptive receiver, to optimally cancel the sampler offset for a lower BER, instead of adjusting dtLevs, the gain of a programmable gain amplifier is adjusted adaptively under fixed dtLevs. The prototype chips including above proposed 10B6Q code and fixed dtLevs are fabricated in 40-nm CMOS technology and tested in chip-on-board assembly. The 10B6Q code only occupies an active area of 0.0009 mm2 with a synthesized gate count of 645. It also consumes 0.23 mW at the operating clock frequency of 667 MHz. The transmitter with 10B6Q code delivers 8-Gb/s PAM-4 signal to the adaptive receiver using fixed dtLevs through a lossy 12-m cable (22-dB channel loss) with a BER of 1E-8, and the eye margin larger than 0.15 UI x 50 mV is measured for a BER of 1E-5. The proto-type chips consume 65.2 mW (excluding PLL), exhibiting an FoM of 0.37 pJ/b/dB. In a second prototype design advanced from the first prototypes, An asymmetric SB transceivers incorporating a 12-Gb/s PAM-4 forward channel and a 125-Mb/s PAM-2 back channel are presented and demonstrated. The proposed wide linear range (WLR) hybrid combined with a gmC low-pass filter and an echo canceller effectively suppresses the outbound signals by more than 24dB. In addition, linear range enhancer which forms a gain attenuator with WLR hybrid breaks the trade-off between the linearity and the amplitude of the PAM-4 signal. The SB transceiver chips are separately fabricated in 40-nm CMOS technology. Using above design techniques, both PAM-4 and PAM-2 SB transceivers achieve BER less than 1E-12 over a 5-m channel (15.9 dB channel loss), consuming 78.4 mW. The overall transceivers achieve an FoM of 0.41 pJ/b/dB and eye margin (at BER of 1E-12) of 0.15 UI and 0.57 UI for the forward PAM-4 and back PAM-2 signals, respectively, under SB communication. This is the best eye margin compared to the prior art SB transceivers with an FoM less than 0.5.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 DISSERTATION ORGANIZATION 4 CHAPTER 2 BACKGROUND ON AUTOMOTIVE CAMERA LINK 6 2.1 OVERVIEW 6 2.2 SYSTEM REQUIREMENTS 10 2.2.1 CHANNEL 10 2.2.2 POWER OVER DIFFERENTIAL LINE (PODL) 12 2.2.3 AC COUPLING AND DC BALANCE CODE 15 2.2.4 SIMULTANEOUS BIDIRECTIONAL COMMUNICATION 18 2.2.4.1 HYBRID 18 2.2.4.2 ECHO CANCELLER 20 2.2.5 ADAPTIVE RECEIVE EQUALIZATION 22 CHAPTER 3 AREA AND POWER EFFICIENT 10B6Q ENCODER FOR DC BALANCE 25 3.1 INTRODUCTION 25 3.2 PRIOR WORKS 28 3.3 PROPOSED AREA- AND POWER-EFFICIENT 10B6Q PAM-4 CODER 30 3.4 DESIGN OF THE 10B6Q CODE 33 3.4.1 PAM-4 DC BALANCE 35 3.4.2 PAM-4 TRANSITION DENSITY 35 3.4.3 10B6Q DECODER 37 3.5 IMPLEMENTATION AND MEASUREMENT RESULTS 40 CHAPTER 4 PAM-4 TRANSMITTER AND ADAPTIVE RECEIVER WITH FIXED DATA AND THRESHOLD LEVELS 45 4.1 INTRODUCTION 45 4.2 PRIOR WORKS 47 4.3 ARCHITECTURE AND IMPLEMENTATION 49 4.2.1 PAM-4 TRANSMITTER 49 4.2.2 PAM-4 ADAPTIVE RECEIVER 52 4.3 MEASUREMENT RESULTS 62 CHAPTER 5 ASYMMETRIC SIMULTANEOUS BIDIRECTIONAL TRANSCEIVERS USING WIDE LINEAR RANGE HYBRID 68 5.1 INTRODUCTION 68 5.2 PRIOR WORKS 70 5.3 WIDE LINEAR RANGE (WLR) HYBRID 75 5.3 IMPLEMENTATION 78 5.3.1 SERIALIZER (SER) DESIGN 78 5.3.2 DESERIALIZER (DES) DESIGN 79 5.4 HALF CIRCUIT ANALYSIS OF WLR HYBRID AND LRE 82 5.5 MEASUREMENT RESULTS 88 CHAPTER 6 CONCLUSION 97 BIBLIOGRAPHY 99 ์ดˆ ๋ก 106๋ฐ•

    Integrated Circuit Design for Hybrid Optoelectronic Interconnects

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    This dissertation focuses on high-speed circuit design for the integration of hybrid optoelectronic interconnects. It bridges the gap between electronic circuit design and optical device design by seamlessly incorporating the compact Verilog-A model for optical components into the SPICE-like simulation environment, such as the Cadence design tool. Optical components fabricated in the IME 130nm SOI CMOS process are characterized. Corresponding compact Verilog-A models for Mach-Zehnder modulator (MZM) device are developed. With this approach, electro-optical co-design and hybrid simulation are made possible. The developed optical models are used for analyzing the system-level specifications of an MZM based optoelectronic transceiver link. Link power budgets for NRZ, PAM-4 and PAM-8 signaling modulations are simulated at system-level. The optimal transmitter extinction ratio (ER) is derived based on the required receiver\u27s minimum optical modulation amplitude (OMA). A limiting receiver is fabricated in the IBM 130 nm CMOS process. By side- by-side wire-bonding to a commercial high-speed InGaAs/InP PIN photodiode, we demonstrate that the hybrid optoelectronic limiting receiver can achieve the bit error rate (BER) of 10-12 with a -6.7 dBm sensitivity at 4 Gb/s. A full-rate, 4-channel 29-1 length parallel PRBS is fabricated in the IBM 130 nm SiGe BiCMOS process. Together with a 10 GHz phase locked loop (PLL) designed from system architecture to transistor level design, the PRBS is demonstrated operating at more than 10 Gb/s. Lessons learned from high-speed PCB design, dealing with signal integrity issue regarding to the PCB transmission line are summarized

    INTEGRATED SINGLE-PHOTON SENSING AND PROCESSING PLATFORM IN STANDARD CMOS

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    Practical implementation of large SPAD-based sensor arrays in the standard CMOS process has been fraught with challenges due to the many performance trade-offs existing at both the device and the system level [1]. At the device level the performance challenge stems from the suboptimal optical characteristics associated with the standard CMOS fabrication process. The challenge at the system level is the development of monolithic readout architecture capable of supporting the large volume of dynamic traffic, associated with multiple single-photon pixels, without limiting the dynamic range and throughput of the sensor. Due to trade-offs in both functionality and performance, no general solution currently exists for an integrated single-photon sensor in standard CMOS single photon sensing and multi-photon resolution. The research described herein is directed towards the development of a versatile high performance integrated SPAD sensor in the standard CMOS process. Towards this purpose a SPAD device with elongated junction geometry and a perimeter field gate that features a large detection area and a highly reduced dark noise has been presented and characterized. Additionally, a novel front-end system for optimizing the dynamic range and after-pulsing noise of the pixel has been developed. The pixel is also equipped with an output interface with an adjustable pulse width response. In order to further enhance the effective dynamic range of the pixel a theoretical model for accurate dead time related loss compensation has been developed and verified. This thesis also introduces a new paradigm for electrical generation and encoding of the SPAD array response that supports fully digital operation at the pixel level while enabling dynamic discrete time amplitude encoding of the array response. Thus offering a first ever system solution to simultaneously exploit both the dynamic nature and the digital profile of the SPAD response. The array interface, comprising of multiple digital inputs capacitively coupled onto a shared quasi-floating sense node, in conjunction with the integrated digital decoding and readout electronics represents the first ever solid state single-photon sensor capable of both photon counting and photon number resolution. The viability of the readout architecture is demonstrated through simulations and preliminary proof of concept measurements

    On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.

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    This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted

    Recent Trends in Communication Networks

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    In recent years there has been many developments in communication technology. This has greatly enhanced the computing power of small handheld resource-constrained mobile devices. Different generations of communication technology have evolved. This had led to new research for communication of large volumes of data in different transmission media and the design of different communication protocols. Another direction of research concerns the secure and error-free communication between the sender and receiver despite the risk of the presence of an eavesdropper. For the communication requirement of a huge amount of multimedia streaming data, a lot of research has been carried out in the design of proper overlay networks. The book addresses new research techniques that have evolved to handle these challenges

    Forward Error Correcting Codes for 100 Gbit/s Optical Communication Systems

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    Design Techniques for Energy Efficient Multi-GB/S Serial I/O Transceivers

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    Total I/O bandwidth demand is growing in high-performance systems due to the emergence of many-core microprocessors and in mobile devices to support the next generation of multi-media features. High-speed serial I/O energy efficiency must improve in order to enable continued scaling of these parallel computing platforms in applications ranging from data centers to smart mobile devices. The first work, a low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase filter. The output driver voltage swing is accurately controlled from 100-200 mV_(ppd) using a low-voltage pseudo-differential regulator that employs a partial negative-resistance load for improved low frequency gain. 1:8 input de-multiplexing is performed at the receiver equalizer output with 8 parallel input samplers clocked from an 8-phase injection-locked oscillator that provides more than 1UI de-skew range. Low-power high-speed serial I/O transmitters which include equalization to compensate for channel frequency dependent loss are required to meet the aggressive link energy efficiency targets of future systems. The second work presents a low power serial link transmitter design that utilizes an output stage which combines a voltage-mode driver, which offers low static-power dissipation, and current-mode equalization, which offers low complexity and dynamic-power dissipation. The utilization of current-mode equalization decouples the equalization settings and termination impedance, allowing for a significant reduction in pre-driver complexity relative to segmented voltage-mode drivers. Proper transmitter series termination is set with an impedance control loop which adjusts the on-resistance of the output transistors in the driver voltage-mode portion. Further reductions in dynamic power dissipation are achieved through scaling the serializer and local clock distribution supply with data rate. Finally, it presents that a scalable quarter-rate transmitter employs an analog-controlled impedance-modulated 2-tap voltage-mode equalizer and achieves fast power-state transitioning with a replica-biased regulator and ILO clock generation. Capacitively-driven 2 mm global clock distribution and automatic phase calibration allows for aggressive supply scaling

    Principles of Neuromorphic Photonics

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    In an age overrun with information, the ability to process reams of data has become crucial. The demand for data will continue to grow as smart gadgets multiply and become increasingly integrated into our daily lives. Next-generation industries in artificial intelligence services and high-performance computing are so far supported by microelectronic platforms. These data-intensive enterprises rely on continual improvements in hardware. Their prospects are running up against a stark reality: conventional one-size-fits-all solutions offered by digital electronics can no longer satisfy this need, as Moore's law (exponential hardware scaling), interconnection density, and the von Neumann architecture reach their limits. With its superior speed and reconfigurability, analog photonics can provide some relief to these problems; however, complex applications of analog photonics have remained largely unexplored due to the absence of a robust photonic integration industry. Recently, the landscape for commercially-manufacturable photonic chips has been changing rapidly and now promises to achieve economies of scale previously enjoyed solely by microelectronics. The scientific community has set out to build bridges between the domains of photonic device physics and neural networks, giving rise to the field of \emph{neuromorphic photonics}. This article reviews the recent progress in integrated neuromorphic photonics. We provide an overview of neuromorphic computing, discuss the associated technology (microelectronic and photonic) platforms and compare their metric performance. We discuss photonic neural network approaches and challenges for integrated neuromorphic photonic processors while providing an in-depth description of photonic neurons and a candidate interconnection architecture. We conclude with a future outlook of neuro-inspired photonic processing.Comment: 28 pages, 19 figure
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