Migration of High Precision PulSAR Analog-to-Digital Converters to Blackfin-based Platforms

This Major Qualifying Project sought to migrate Analog Devices\u27 PulSAR line of ADCs to a more modern testing and evaluation platform, the SDP. The project resulted in more extensible daughter cards, a modular driver amplifier system, an integrated power supply design, and a software package to read and analyze the ADC data. Reference schematics were also developed and tested to showcase high performance and low power with the PulSAR converters

Built-in self test of high speed analog-to-digital converters

Signals found in nature need to be converted to the digital domain through analog-to-digital converters (ADCs) to be processed by digital means [1]. For applications in communication and measurement [2], [3], high conversion rates are required. With advances of the complementary metal oxide semiconductor (CMOS) technology, the conversion rates of CMOS ADCs are now well beyond the gigasamples per second (GS/s) range, but only moderate resolutions are required [4]. These ADCs need to be tested after fabrication and, if possible, during field operation. The test costs are a very significant fraction of their production cost [5]. This is mainly due to lengthy use of very expensive automated test equipment (ATE) to apply specific test stimuli to the devices under test (DUT) and to collect and analyze their responses.publishe

Alternative Methods for Non-Linearity Estimation in High-Resolution Analog-to-Digital Converters

The evaluation of the linearity performance of a high resolution Analog-to- Digital Converter (ADC) by the Standard Histogram method is an outstanding challenge due to the requirement of high purity of the input signal and the high number of output data that must be acquired to obtain an acceptable accuracy on the estimation. These requirements become major application drawbacks when the measures have to be performed multiple times within long test flows and for many parts, and under an industrial environment that seeks to reduce costs and lead times as is the case in the New Space sector. This thesis introduces two alternative methods that succeed in relaxing the two previous requirements for the estimation of the Integral Nonlinearity (INL) parameter in ADCs. The methods have been evaluated by estimating the Integral Non-Linearity pattern by simulation using realistic high-resolution ADC models and experimentally by applying them to real high performance ADCs. First, the challenge of applying the Standard Histogram method for the evaluation of static parameters in high resolution ADCs and how the drawbacks are accentuated in the New Space industry is analysed, being a highly expensive method for an industrial environment where cost and lead time reduction is demanded. Several alternative methods to the Standard Histogram for estimating Integral Nonlinearity in high resolution ADCs are reviewed and studied. As the number of existing works in the literature is very large and addressing all of them is a challenge in itself, only those most relevant to the development of this thesis have been included. Methods based on spectral processing to reduce the number of data acquired for the linearity test and methods based on a double histogram to be able to use generators that do not meet the the purity requirement against the ADC to be tested are further analysed. Two novel contributions are presented in this work for the estimation of the Integral Nonlinearity in ADCs, as possible alternatives to the Standard Histogram method. The first method, referred to as SSA (Simple Spectral Approach), seeks to reduce the number of output data that need to be acquired and focuses on INL estimation using an algorithm based on processing the spectrum of the output signal when a sinusoidal input stimulus is used. This type of approach requires a much smaller number of samples than the Standard Histogram method, although the estimation accuracy will depend on how smooth or abrupt the ADC nonlinearity pattern is. In general, this algorithm cannot be used to perform a calibration of the ADC nonlinearity error, but it can be applied to find out between which limits it lies and what its approximate shape is. The second method, named SDH (Simplified Double Histogram)aims to estimate the Non-Linearity of the ADC using a poor linearity generator. The approach uses two histograms constructed from the two set of output data in response to two identical input signals except for a dc offset between them. Using a simple adder model, an extended approach named ESDH (Extended Simplified Double Histogram) addresses and corrects for possible time drifts during the two data acquisitions, so that it can be successfully applied in a non-stationary test environment. According to the experimental results obtained, the proposed algorithm achieves high estimation accuracy. Both contributions have been successfully tested in high-resolution ADCs with both simulated and real laboratory experiments, the latter using a commercial ADC with 14-bit resolution and 65Msps sampling rate (AD6644 from Analog Devices).La medida de la característica de linealidad de un convertidor analógicodigital (ADC) de alta resolución mediante el método estándar del Histograma constituye un gran desafío debido los requisitos de alta pureza de la señal de entrada y del elevado número de datos de salida que deben adquirirse para obtener una precisión aceptable en la estimación. Estos requisitos encuentran importantes inconvenientes para su aplicación cuando las medidas deben realizarse dentro de largos flujos de pruebas, múltiples veces y en un gran número de piezas, y todo bajo un entorno industrial que busca reducir costes y plazos de entrega como es el caso del sector del Nuevo Espacio. Esta tesis introduce dos métodos alternativos que consiguen relajar los dos requisitos anteriores para la estimación de los parámetros de no linealidad en los ADCs. Los métodos se han evaluado estimando el patrón de No Linealidad Integral (INL) mediante simulación utilizando modelos realistas de ADC de alta resolución y experimentalmente aplicándolos en ADCs reales. Inicialmente se analiza el reto que supone la aplicación del método estándar del Histograma para la evaluación de los parámetros estáticos en ADCs de alta resolución y cómo sus inconvenientes se acentúan en la industria del Nuevo Espacio, siendo un método altamente costoso para un entorno industrial donde se exige la reducción de costes y plazos de entrega. Se estudian métodos alternativos al Histograma estándar para la estimación de la No Linealidad Integral en ADCs de alta resolución. Como el número de trabajos es muy amplio y abordarlos todos es ya en sí un desafío, se han incluido aquellos más relevantes para el desarrollo de esta tesis. Se analizan especialmente los métodos basados en el procesamiento espectral para reducir el número de datos que necesitan ser adquiridos y los métodos basados en un doble histograma para poder utilizar generadores que no cumplen el requisito de precisión frente al ADC a medir. En este trabajo se presentan dos novedosas aportaciones para la estimación de la No Linealidad Integral en ADCs, como posibles alternativas al método estándar del Histograma. El primer método, denominado SSA (Simple Spectral Approach), busca reducir el número de datos de salida que es necesario adquirir y se centra en la estimación de la INL mediante un algoritmo basado en el procesamiento del espectro de la señal de salida cuando se utiliza un estímulo de entrada sinusoidal. Este tipo de enfoque requiere un número mucho menor de muestras que el método estándar del Histograma, aunque la precisión de la estimación dependerá de lo suave o abrupto que sea el patrón de no-linealidad del ADC a medir. En general, este algoritmo no puede utilizarse para realizar una calibración del error de no linealidad del ADC, pero puede aplicarse para averiguar entre qué límites se encuentra y cuál es su forma aproximada. El segundo método, denominado SDH (Simplified Double Histogram) tiene como objetivo estimar la no linealidad del ADC utilizando un generador de baja pureza. El algoritmo utiliza dos histogramas, construidos a partir de dos conjuntos de datos de salida en respuesta a dos señales de entrada idénticas, excepto por un desplazamiento constante entre ellas. Utilizando un modelo simple de sumador, un enfoque ampliado denominado ESDH (Extended Simplified Double Histogram) aborda y corrige las posibles derivas temporales durante las dos adquisiciones de datos, de modo que puede aplicarse con éxito en un entorno de prueba no estacionario. De acuerdo con los resultados experimentales obtenidos, el algoritmo propuesto alcanza una alta precisión de estimación. Ambas contribuciones han sido probadas en ADCs de alta resolución con experimentos tanto simulados como reales en laboratorio, estos últimos utilizando un ADC comercial con una resolución de 14 bits y una tasa de muestreo de 65Msps (AD6644 de Analog Devices)

Evaluation Of 28nm 10 Bit Adc Using Ramp And Sinusoidal Histogram Methodologies

ADC production testing has become more challenging due to more stringent test procedure for new generation of ADC. The trend for silicon cost is going down while the cost of test is going up. Therefore, to reduce the cost of test and preserve the test accuracy is essential for high volume testing in production. This research is conducted for accurate ADC testing using histogram methodologies. Histogram methodology is the most common test procedure used in high volume production testing. In the past there were a lot of studies on testing the ADC but there were no emphasizing on various histogram methodologies for high volume testing. This research objective is to develop test solutions for 28nm 10 bit ADC using histogram methodologies. The outcome from this research has clearly shows that the test program that has been developed is able to segregate the good and bad devices. 98.18% of the devices are able to pass the ADC testing while remaining 1.82% fail the ADC test. It was found that Ramp Histogram and Sinusoidal Histogram method has achieved this research objective as both methodologies shows similar result based on comparison that has been made. It was known that accurate ADC testing requires large sample size. This research found that multi-site testing was able to compensate the drawback in histogram methodologies. The result shows that multi-site testing is 63.72% more efficient in term of ADC testing time

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

ADC Testing in Standard and Non-standard Ways, Executed in a Unified Framework

Several test methods are available to examine static and dynamic properties of analog to digital converters (ADCs). The most robust and straightforward ones are codified in international standards released by the IEEE, or by the IEC. These methods have been improved based on ideas proposed in scientific papers published in the field of ADC testing. However, there are algorithms and test techniques that are not yet standardized, but could be very useful to achieve more information concerning the device under test. These are predominantly amendments of the standard methods, elaborated to increase the accuracy, robustness, computation demand, etc. Nevertheless, it is important to be able to test ADCs strictly according to the standards, and it can also be important to use methods that go beyond the standardized ones in some aspects. This paper presents an idea to harmonize standard and non standard ADC test methods in a single software tool on widely used platform