High Current Density Low Voltage Isolated Dc-dc Converterswith Fast Transient Response

With the rapid development of microprocessor and semiconductor technology, industry continues to update the requirements for power supplies. For telecommunication and computing system applications, power supplies require increasing current level while the supply voltage keeps decreasing. For example, the Intel\u27s CPU core voltage decreased from 2 volt in 1999 to 1 volt in 2005 while the supply current increased from 20A in 1999 to up to 100A in 2005. As a result, low-voltage high-current high efficiency dc-dc converters with high power-density are demanded for state-of-the-art applications and also the future applications. Half-bridge dc-dc converter with current-doubler rectification is regarded as a good topology that is suitable for high-current low-voltage applications. There are three control schemes for half-bridge dc-dc converters and in order to provide a valid unified analog model for optimal compensator design, the analog state-space modeling and small signal modeling are studied in the dissertation and unified state-space and analog small signal model are derived. In addition, the digital control gains a lot of attentions due to its flexibility and re-programmability. In this dissertation, a unified digital small signal model for half-bridge dc-dc converter with current doubler rectifier is also developed and the digital compensator based on the derived model is implemented and verified by the experiments with the TI DSP chip. In addition, although current doubler rectifier is widely used in industry, the key issue is the current sharing between two inductors. The current imbalance is well studied and solved in non-isolated multi-phase buck converters, yet few discusse this issue in the current doubler rectification topology within academia and industry. This dissertation analyze the current sharing issue in comparison with multi-phase buck and one modified current doubler rectifier topology is proposed to achieve passive current sharing. The performance is evaluated with half bridge dc-dc converter; good current sharing is achieved without additional circuitry. Due to increasing demands for high-efficiency high-power-density low-voltage high current topologies for future applications, the thermal management is challenging. Since the secondary-side conduction loss dominates the overall power loss in low-voltage high-current isolated dc-dc converters, a novel current tripler rectification topology is proposed. Theoretical analysis, comparison and experimental results verify that the proposed rectification technique has good thermal management and well-distributed power dissipation, simplified magnetic design and low copper loss for inductors and transformer. That is due to the fact that the load current is better distributed in three inductors and the rms current in transformer windings is reduced. Another challenge in telecommunication and computing applications is fast transient response of the converter to the increasing slew-rate of load current change. For instance, from Intel\u27s roadmap, it can be observed that the current slew rate of the age regulator has dramatically increased from 25A/uS in 1999 to 400A/us in 2005. One of the solutions to achieve fast transient response is secondary-side control technique to eliminate the delay of optocoupler to increase the system bandwidth. Active-clamp half bridge dc-dc converter with secondary-side control is presented and one industry standard 16th prototype is built and tested; good efficiency and transient response are shown in the experimental section. However, one key issue for implementation of secondary-side control is start-up. A new zero-voltage-switching buck-flyback isolated dc-dc converter with synchronous rectification is proposed, and it is only suitable for start-up circuit for secondary-side controlled converter, but also for house-keeping power supplies and standalone power supplies requiring multi-outputs

Generalized self-driven AC-DC synchronous rectification techniques for single- and multiphase systems

This paper extends the single-phase self-driven synchronous rectification (SDSR) technique to multiphase ac-dc systems. Power MOSFETs with either voltage- or current-sensing self-driven gate drives are used to replace the diodes in the rectifier circuits. The generalized methodology allows multiphase SDSRs to be designed to replace the multiphase diode rectifiers. Unlike the traditional SR that is designed for high-frequency power converters, the SDSR proposed here can be a direct replacement of the power diode bridges for both low- and high-frequency operations. The SDSR utilizes its output dc voltage to supply power to its control circuit. No start-up control is needed because the body diodes of the power MOSFETs provide the diode rectifier for the initial start-up stage. The generalized method is demonstrated in 2-kW one-phase and three-phase SDSRs for inductive, capacitive, and resistive loads. Power loss reduction in the range of 50%-69% has been achieved for the resistive load. © 2009 IEEE.published_or_final_versio

Switched-capacitor step-down rectifier for low-voltage power conversion

This paper presents a switched-capacitor rectifier that provides step down voltage conversion from an ac input voltage to a dc output. Coupled with current-drive source, low-loss and high step-down rectification is realized. Implementation in CMOS with appropriate controls results in a design suitable for low-voltage very-high-frequency conversion. Applications include switched-capacitor rectification to convert high-frequency ac to a dc output and, combined with inversion and transformation, to dc-dc converters for low-voltage outputs. A two-step CMOS integrated full-bridge switched-capacitor rectifier is implemented in TSMC 0.25 μm CMOS technology for demonstration purposes. For an operation frequency of 50 MHz and an output voltage of 2.5 V, the peak efficiency of the rectifier is 81% at a power level of 4 W.Interconnect Focus Center (United States. Defense Advanced Research Projects Agency and Semiconductor Research Corporation

Control And Topology Improvements In Half-bridge Dc-dc Converters

Efficiency and transient response are two key requirements for DC-DC converters. Topology and control are two key topics in this dissertation. A variety of techniques for DC-DC converter performance improvement are presented in this work. Focusing on the efficiency issue, a variety of clamping techniques including both active and passive methods are presented after the ringing issues in DC-DC converters are investigated. By presenting the clamping techniques, a big variety of energy management concepts are introduced. The active bridge-capacitor tank clamping and FET-diode-capacitor tank clamping are close ideas, which transfer the leakage inductor energy to clamping capacitor to prevent oscillation between leakage inductor and junction capacitor of MOSFETs. The two-FET-clamping tank employs two MOSFETs to freewheeling the leakage current when the main MOSFETs of the half-bridge are both off. Driving voltage variation on the secondary side Synchronous Rectifier (SR) MOSFETs in self-driven circuit due to input voltage variation in bus converter applications is also investigated. One solution with a variety of derivations is proposed using zerner-capacitor combination to clamping the voltage while maintaining reasonable power losses. Another efficiency improvement idea comes from phase-shift concept in DC-DC converters. By employing phase-shift scheme, the primary side and the secondary side two MOSFETs have complementary driving signals respectively, which allow the MOSFET to be turned on with Zero Voltage Switching (ZVS). Simulation verified the feasibility of the proposed phase-shifted DC-DC converter. From the control scheme point of view, a novel peak current mode control concept for half-bridge topologies is presented. Aiming at compensating the imbalanced voltage due to peak current mode control in symmetric half-bridge topologies, an additional voltage compensation loop is used to bring the half-bridge capacitor voltage back to balance. In the proposed solutions, one scheme is applied on symmetric half-bridge topology and the other one is applied on Duty-cycle-shifted (DCS) half-bridge topology. Both schemes employ simple circuitry and are suitable for integration. Loop stability issues are also investigated in this work. Modeling work shows the uncompensated half-bridge topology cannot be stabilized under all conditions and the additional compensation loop helps to prevent the voltage imbalance effectively

A Practical Approach to the Design of a Highly Efficient PSFB DC-DC Converter for Server Applications

The phase shift full bridge (PSFB) is a widely known isolated DC-DC converter topology commonly used in medium to high power applications, and one of the best candidates for the front-end DC-DC converter in server power supplies. Since the server power supplies consume an enormous amount of power, the most critical issue is to achieve high efficiency. Several organizations promoting electrical energy efficiency, like the 80 PLUS, keep introducing higher efficiency certifications with growing requirements extending also to light loads. The design of a high efficiency PSFB converter is a complex problem with many degrees of freedom which requires of a sufficiently accurate modeling of the losses and of e cient design criteria. In this work a losses model of the converter is proposed as well as design guidelines for the efficiency optimization of PSFB converter. The model and the criteria are tested with the redesign of an existing reference PSFB converter of 1400 W for server applications, with wide input voltage range, nominal 400 V input and 12 V output; achieving 95.85% of efficiency at 50% of the load. A new optimized prototype of PSFB was built with the same specifications, achieving a peak efficiency of 96.68% at 50% of the load.This research was financed by Infineon Technologies AG

A Step-Down ZVS Power Converter with Self-Driven Synchronous Rectifier

©2021 IEEE. This is the accepted manuscript version of an article which has been published in final form at https://dx.doi.org/10.1109/ISCAS51556.2021.9401563In this paper a step-down ZVS power converter with a self-driven synchronous rectifier (SDSR) for a low-voltage high-current applications is proposed. A transformer leakage inductance, a resonant capacitor and a diode make up the active resonant network. To improve the performance of the converter, a SDSR with a center-tapped transformer is used at the secondary side of the converter. Consequently, due to transformer leakage inductance in secondary side, the output section requires no additional inductor, leading to a major size reduction of the circuit. For verification purposes, a laboratory prototype of the proposed converter is manufactured. Experimental results are presented for waveforms to validate the theoretical outcomes

Modulation scheme for the bidirectional operation of the Phase Shift Full Bridge Power Converter

This paper proposes a novel modulation technique for the bidirectional operation of the Phase Shift Full Bridge (PSFB) DC/DC power converter. The forward or buck operation of this topology is well known and widely used in medium to high power DC to DC converter applications. In contrast, backward or boost operation is less typical since it exhibits large drain voltage overshoot in devices located at the secondary or current-fed side; a known problem in isolated boost converters. For that reason other topologies of symmetric configuration are preferred in bidirectional applications, like CLLC resonant converter or Dual Active Bridge (DAB). In this work, we propose a modulation technique overcoming the drain voltage overshoot of the isolated boost converter at the secondary or current-fed side, without additional components other than the ones in a standard PSFB and still achieving full or nearly full ZVS in the primary or voltage-fed side along all the load range of the converter. The proposed modulation has been tested in a bidirectional 3.3 kW PSFB with 400 V input and 54.5 V output, achieving a 98 % of peak efficiency in buck mode and 97.5 % in boost mode operation. This demonstrates that the PSFB converter may become a relatively simple and efficient topology for bidirectional DC to DC converter applications

Digital Control Of Half-Bridge Dc-Dc Converters With Current Doubler Rectification

DC-DC power converters play an important role in powering telecom and computing systems. Complex systems, including power electronics systems, are increasingly using digital controllers because of the major advancements in digital controllers and DSP as well as there ability to perform sophisticated and enhanced control schemes. In this thesis, the digital controller is investigated for DC-DC converters in high current low voltage applications. For an optimal design of a regulated DC-DC converter, it is necessary to derive a valid model. The current doubler rectified half bridge (CDRHB) DC-DC converter is suitable for high current low voltage applications. In this thesis, the topology operations are analyzed and then the unified state space model, analog small signal model and digital small signal model are derived. Then the digital compensator design is discussed as well as the analog-digital converter (ADC) and the digital pulse-width-modulator (DPWM) design rules. In addition, voltage driving optimization is proposed for the benefit of the digital controller. Finally, experimental results based on the CDRHB are presented and analyzed