DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

Internet of robotic things : converging sensing/actuating, hypoconnectivity, artificial intelligence and IoT Platforms

The Internet of Things (IoT) concept is evolving rapidly and influencing newdevelopments in various application domains, such as the Internet of MobileThings (IoMT), Autonomous Internet of Things (A-IoT), Autonomous Systemof Things (ASoT), Internet of Autonomous Things (IoAT), Internetof Things Clouds (IoT-C) and the Internet of Robotic Things (IoRT) etc.that are progressing/advancing by using IoT technology. The IoT influencerepresents new development and deployment challenges in different areassuch as seamless platform integration, context based cognitive network integration,new mobile sensor/actuator network paradigms, things identification(addressing, naming in IoT) and dynamic things discoverability and manyothers. The IoRT represents new convergence challenges and their need to be addressed, in one side the programmability and the communication ofmultiple heterogeneous mobile/autonomous/robotic things for cooperating,their coordination, configuration, exchange of information, security, safetyand protection. Developments in IoT heterogeneous parallel processing/communication and dynamic systems based on parallelism and concurrencyrequire new ideas for integrating the intelligent “devices”, collaborativerobots (COBOTS), into IoT applications. Dynamic maintainability, selfhealing,self-repair of resources, changing resource state, (re-) configurationand context based IoT systems for service implementation and integrationwith IoT network service composition are of paramount importance whennew “cognitive devices” are becoming active participants in IoT applications.This chapter aims to be an overview of the IoRT concept, technologies,architectures and applications and to provide a comprehensive coverage offuture challenges, developments and applications

Adaptive Process Management in Cyber-Physical Domains

The increasing application of process-oriented approaches in new challenging cyber-physical domains beyond business computing (e.g., personalized healthcare, emergency management, factories of the future, home automation, etc.) has led to reconsider the level of flexibility and support required to manage complex processes in such domains. A cyber-physical domain is characterized by the presence of a cyber-physical system coordinating heterogeneous ICT components (PCs, smartphones, sensors, actuators) and involving real world entities (humans, machines, agents, robots, etc.) that perform complex tasks in the “physical” real world to achieve a common goal. The physical world, however, is not entirely predictable, and processes enacted in cyber-physical domains must be robust to unexpected conditions and adaptable to unanticipated exceptions. This demands a more flexible approach in process design and enactment, recognizing that in real-world environments it is not adequate to assume that all possible recovery activities can be predefined for dealing with the exceptions that can ensue. In this chapter, we tackle the above issue and we propose a general approach, a concrete framework and a process management system implementation, called SmartPM, for automatically adapting processes enacted in cyber-physical domains in case of unanticipated exceptions and exogenous events. The adaptation mechanism provided by SmartPM is based on declarative task specifications, execution monitoring for detecting failures and context changes at run-time, and automated planning techniques to self-repair the running process, without requiring to predefine any specific adaptation policy or exception handler at design-time

Fault-tolerant fpga for mission-critical applications.

One of the devices that play a great role in electronic circuits design, specifically safety-critical design applications, is Field programmable Gate Arrays (FPGAs). This is because of its high performance, re-configurability and low development cost. FPGAs are used in many applications such as data processing, networks, automotive, space and industrial applications. Negative impacts on the reliability of such applications result from moving to smaller feature sizes in the latest FPGA architectures. This increases the need for fault-tolerant techniques to improve reliability and extend system lifetime of FPGA-based applications. In this thesis, two fault-tolerant techniques for FPGA-based applications are proposed with a built-in fault detection region. A low cost fault detection scheme is proposed for detecting faults using the fault detection region used in both schemes. The fault detection scheme primarily detects open faults in the programmable interconnect resources in the FPGAs. In addition, Stuck-At faults and Single Event Upsets (SEUs) fault can be detected. For fault recovery, each scheme has its own fault recovery approach. The first approach uses a spare module and a 2-to-1 multiplexer to recover from any fault detected. On the other hand, the second approach recovers from any fault detected using the property of Partial Reconfiguration (PR) in the FPGAs. It relies on identifying a Partially Reconfigurable block (P_b) in the FPGA that is used in the recovery process after the first faulty module is identified in the system. This technique uses only one location to recover from faults in any of the FPGA’s modules and the FPGA interconnects. Simulation results show that both techniques can detect and recover from open faults. In addition, Stuck-At faults and Single Event Upsets (SEUs) fault can also be detected. Finally, both techniques require low area overhead

The current crisis of intensive work regimes and the question of social exclusion in industrialized countries

The aim of this article is to analyze the difficulties currently being faced by regimes of social regulation of economic life and the ways in which they are being transformed. In order to address this complex question, transformations in the labour market are examined. Emphasis is given in particular to the fact that the decline in life-time jobs has had a destabilizing impact on employment systems. This is true not so much in terms of reduced employment. In fact, numerous job opportunities have been created in the tertiary sector, though insecure and badly paid, but these jobs do not reflect the traditional standards of social regulation and therefore entail a weakening of the mechanisms of social integration and a growing risk of exclusion. At this point the theme of the heterogeneity and polarization of working careers in service society is introduced, highlighting in particular the variety of regulatory forms with their different and changing mixes of family, state and market. These policy mixes form the basis for the various models of welfare capitalism identified here. Finally, consideration is given to the two main responses to this transitional phase in industrialized countries. On the one hand, in English-speaking countries which are characterised by intensive deregulation and the spread of flexible forms of work; on the other hand, in the countries of continental Europe where the redistributive modes of traditional welfare programmes have been preserved. Neither of these strategies, however, has produced new and lasting prospects for synergies between the economy and the society. Potential regulatory innovations would presuppose a reappraisal of modes of activity that are at present 'invisible' such as production for own consumption, family care, volunteer and charitable work and the creation of social capital. Political steps in this direction could lead to a new balance between state, market and family that would secure the level of cooperation needed for socially embedded economic life. -- Der Aufsatz analysiert die gegenwärtigen Schwierigkeiten, mit denen verschiedene Regimes sozialer Regulierung der Wirtschaft konfrontiert sind, einschließlich ihrer Transformationspfade. Um dieser komplexen Fragestellung gerecht zu werden, werden zunächst die allgemeinen Veränderungsprozesse auf dem Arbeitsmarkt dargestellt. Besonderes Gewicht wird dabei auf die Tatsache gelegt, daß der Abbau von lebenslangen Arbeitsverhältnissen das Beschäftigungssystem massiv destabilisiert. Das bezieht sich nicht ausschließlich oder gar vorrangig auf die rückläufigen Beschäftigungsmöglichkeiten. Gleichzeitig sind nämlich im Dienstleistungssektor zahlreiche neue Arbeitsplätze entstanden - wenn auch in der Regel unsichere und schlecht bezahlte. Sie spiegeln ein geringeres Maß gesellschaftlicher Regulierung und implizieren damit eine schwächere soziale Integration sowie ein höheres Risiko sozialer Ausgrenzung. In diesem Zusammenhang werden die Trends zur Heterogenisierung und Polarisierung der Berufsbiographien in der Dienstleistungsgesellschaft thematisiert und dabei besonders die Vielfalt der länderspezifischen Mischungen von Zuständigkeiten von Familie, Staat und Markt dargelegt. Diese bilden die Grundlage für die in diesem Beitrag identifizierten Modelle wohlfahrtsstaatlicher Kapitalismen. Es lassen sich zwei verschiedene Reaktionsmuster der Industriestaaten auf diese Veränderungsprozesse unterscheiden. Auf der einen Seite stehen USA und Großbritannien mit ihren ausgeprägten Deregulierungspolitiken und der Ausweitung von flexiblen Arbeitsverhältnissen; auf der anderen Seite die Länder Kontinentaleuropas, die auf die Beibehaltung der Transferorientierung traditioneller Wohlfahrtsprogramme setzen. Keine dieser Strategien führte jedoch zu neuen und dauerhaften Synergie-Effekten zwischen Wirtschaft und Gesellschaft. Die Möglichkeiten für innovative Regulierungen - so die hier vertretene These - sind daran gebunden, daß bislang 'unsichtbare' Produktionen aufgewertet werden, wie beispielsweise Produktion zum Eigenverbrauch, unbezahlte Tätigkeiten wie Familienarbeit, Solidarität und die Bildung von sozialem Kapital. Ein solcher Ansatz könnte richtungsweisend sein für ein neues regulatives Gleichgewicht, das den Mindestanforderungen an Kooperation Rechnung trägt und damit die Voraussetzung für ein sozial integriertes Wirtschaftsleben gewährleistet.

A Multi-layer Fpga Framework Supporting Autonomous Runtime Partial Reconfiguration

Partial reconfiguration is a unique capability provided by several Field Programmable Gate Array (FPGA) vendors recently, which involves altering part of the programmed design within an SRAM-based FPGA at run-time. In this dissertation, a Multilayer Runtime Reconfiguration Architecture (MRRA) is developed, evaluated, and refined for Autonomous Runtime Partial Reconfiguration of FPGA devices. Under the proposed MRRA paradigm, FPGA configurations can be manipulated at runtime using on-chip resources. Operations are partitioned into Logic, Translation, and Reconfiguration layers along with a standardized set of Application Programming Interfaces (APIs). At each level, resource details are encapsulated and managed for efficiency and portability during operation. An MRRA mapping theory is developed to link the general logic function and area allocation information to the device related physical configuration level data by using mathematical data structure and physical constraints. In certain scenarios, configuration bit stream data can be read and modified directly for fast operations, relying on the use of similar logic functions and common interconnection resources for communication. A corresponding logic control flow is also developed to make the entire process autonomous. Several prototype MRRA systems are developed on a Xilinx Virtex II Pro platform. The Virtex II Pro on-chip PowerPC core and block RAM are employed to manage control operations while multiple physical interfaces establish and supplement autonomous reconfiguration capabilities. Area, speed and power optimization techniques are developed based on the developed Xilinx prototype. Evaluations and analysis of these prototype and techniques are performed on a number of benchmark and hashing algorithm case studies. The results indicate that based on a variety of test benches, up to 70% reduction in the resource utilization, up to 50% improvement in power consumption, and up to 10 times increase in run-time performance are achieved using the developed architecture and approaches compared with Xilinx baseline reconfiguration flow. Finally, a Genetic Algorithm (GA) for a FPGA fault tolerance case study is evaluated as a ultimate high-level application running on this architecture. It demonstrated that this is a hardware and software infrastructure that enables an FPGA to dynamically reconfigure itself efficiently under the control of a soft microprocessor core that is instantiated within the FPGA fabric. Such a system contributes to the observed benefits of intelligent control, fast reconfiguration, and low overhead

Injecting FPGA Configuration Faults in Parallel

When using SRAM-based FPGA devices in safety critical applications testing against bitflips in the device configuration memory is essential. Often such tests are achieved by corrupting configuration memory bits of a running device, but this has many scalability, reliability, and flexibility challenges. In this paper, we present a framework and a concrete implementation of a parallel fault injection cluster that addresses these challenges. Scalability is addressed by using multiple identical FPGA devices, each testing a different region in parallel. Reliability is addressed by using reconfigurable system-on-chip devices, that are isolated from each other. Flexibility is addressed by using a pending commit structure, that continually checkpoints the overall experiment and allows elastic scaling. We test and showcase our approach by exhaustively flipping every bit in the configuration memory of the CHStone benchmark suite and a VivadoHLS generated k-means clustering image processing application. Our results show that: linear scaling is possible as the number of devices increases; the majority of error inducing bitflips in the k-means application do not significantly impact the output; and that the Xilinx Essential bits tool may miss some bits that can induce errors