Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)

ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability

Application of mainstream object relational database to real time database applications in industrial automation

This thesis examines the proposition that because of recent huge increases in processing power, disk and memory capacities the commercial mainstream object relational databases may now be a viable option to replace dedicated real-time databases in industrial automation. The benefits are lower product cost, greater availability of trained manpower for development and maintenance and lower risks due to larger installed base and larger number of platforms supported. The issues considered in testing this proposition were performance, ability to mimic critical real-time database features, replication of the real-time database application development and administration tools and finally the low overhead high speed, real-time data compression facility available in real-time databases. An efficient yet simple real-time compression algorithm was developed for use with relational databases and benchmarked. Extensive comparative benchmarking has been done to convincingly prove the proposition. The results overwhelmingly show, that for a majority of industrial real-time database applications, the performance offered by a commercial object relational database on a current platform are more than adequate

Technology 2003: The Fourth National Technology Transfer Conference and Exposition, volume 2

Proceedings from symposia of the Technology 2003 Conference and Exposition, Dec. 7-9, 1993, Anaheim, CA, are presented. Volume 2 features papers on artificial intelligence, CAD&E, computer hardware, computer software, information management, photonics, robotics, test and measurement, video and imaging, and virtual reality/simulation

Smart real time operating system

Ph.DDOCTOR OF PHILOSOPH

Design of a fault-tolerant journalized architecture for a stack processor

Dans cette thèse, nous proposons une nouvelle approche pour la conception d'un processeur tolérant aux fautes. Celle-ci répond à plusieurs objectifs dont celui d'obtenir un niveau de protection élevé contre les erreurs transitoires et un compromis raisonnable entre performances temporelles et coût en surface. Le processeur résultant sera utilisé ultérieurement comme élément constitutif d'un système multiprocesseur sur puce (MPSoC) tolérant aux fautes. Les concepts mis en œuvre pour la tolérance aux fautes reposent sur l'emploi de techniques de détection concurrente d'erreurs et de recouvrement par réexécution. Les éléments centraux de la nouvelle architecture sont, un cœur de processeur à pile de données de type MISC (Minimal Instruction Set Computer) capable d'auto-détection d'erreurs, et un mécanisme matériel de journalisation chargé d'empêcher la propagation d'erreurs vers la mémoire centrale (supposée sûre) et de limiter l'impact du mécanisme de recouvrement sur les performances temporelles. L'approche méthodologique mise en œuvre repose sur la modélisation et la simulation selon différents modes et niveaux d'abstraction, le développement d'outils logiciels dédiées, et le prototypage sur des technologies FPGA. Les résultats, obtenus sans recherche d'optimisation poussée, montrent clairement la pertinence de l'approche proposée, en offrant un bon compromis entre protection et performances. En effet, comme le montrent les multiples campagnes d'injection d'erreurs, le niveau de tolérance au fautes est élevé avec 100% des erreurs simples détectées et recouvrées et environ 60% et 78% des erreurs doubles et triples. Le taux recouvrement reste raisonnable pour des erreurs à multiplicité plus élevée, étant encore de 36% pour des erreurs de multiplicité 8In this thesis, we propose a new approach to designing a fault tolerant processor. The methodology is addressing several goals including high level of protection against transient faults along with reasonable performance and area overhead trade-offs. The resulting fault-tolerant processor will be used as a building block in a fault tolerant MPSoC (Multi-Processor System-on-Chip) architecture. The concepts being used to achieve fault tolerance are based on concurrent detection and rollback error recovery techniques. The core elements in this architecture are a stack processor core from the MISC (Minimal Instruction Set Computer) class and a hardware journal in charge of preventing error propagation to the main memory (supposedly dependable) and limiting the impact of the rollback mechanism on time performance. The design methodology relies on modeling at different abstraction levels and simulating modes, developing dedicated software tools, and prototyping on FPGA technology. The results, obtained without seeking a thorough optimization, show clearly the relevance of the proposed approach, offering a good compromise in terms of protection and performance. Indeed, fault tolerance, as revealed by several error injection campaigns, prove to be high with 100% of errors being detected and recovered for single bit error patterns, and about 60% and 78% for double and triple bit error patterns, respectively. Furthermore, recovery rate is still acceptable for larger error patterns, with yet a recovery rate of 36%on 8 bit error pattern