Aspects of practical implementations of PRAM algorithms

The PRAM is a shared memory model of parallel computation which abstracts away from inessential engineering details. It provides a very simple architecture independent model and provides a good programming environment. Theoreticians of the computer science community have proved that it is possible to emulate the theoretical PRAM model using current technology. Solutions have been found for effectively interconnecting processing elements, for routing data on these networks and for distributing the data among memory modules without hotspots. This thesis reviews this emulation and the possibilities it provides for large scale general purpose parallel computation. The emulation employs a bridging model which acts as an interface between the actual hardware and the PRAM model. We review the evidence that such a scheme crn achieve scalable parallel performance and portable parallel software and that PRAM algorithms can be optimally implemented on such practical models. In the course of this review we presented the following new results: 1. Concerning parallel approximation algorithms, we describe an NC algorithm for finding an approximation to a minimum weight perfect matching in a complete weighted graph. The algorithm is conceptually very simple and it is also the first NC-approximation algorithm for the task with a sub-linear performance ratio. 2. Concerning graph embedding, we describe dense edge-disjoint embeddings of the complete binary tree with n leaves in the following n-node communication networks: the hypercube, the de Bruijn and shuffle-exchange networks and the 2-dimcnsional mesh. In the embeddings the maximum distance from a leaf to the root of the tree is asymptotically optimally short. The embeddings facilitate efficient implementation of many PRAM algorithms on networks employing these graphs as interconnection networks. 3. Concerning bulk synchronous algorithmics, we describe scalable transportable algorithms for the following three commonly required types of computation; balanced tree computations. Fast Fourier Transforms and matrix multiplications

Designing a large scale switch interconnection architecture and a study of ATM scheduling algorithms.

by Yee Ka Chi.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 101-[106]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.1.1 --- Large Scale Switch Interconnections --- p.2Chapter 1.1.2 --- Multichannel Switching and Resequencing --- p.6Chapter 1.1.3 --- Scheduling --- p.7Chapter 2 --- Hierarchical Banyan Switch Interconnection --- p.12Chapter 2.1 --- Introduction --- p.12Chapter 2.2 --- Switch Architecture --- p.13Chapter 2.3 --- Switch Operation --- p.19Chapter 2.3.1 --- Call Setup --- p.19Chapter 2.3.2 --- Cell Routing --- p.21Chapter 2.3.3 --- Fault Tolerance --- p.27Chapter 2.4 --- Call Blocking Analysis --- p.28Chapter 2.4.1 --- Dilated Banyan --- p.29Chapter 2.4.2 --- Dilated Benes Network --- p.30Chapter 2.4.3 --- HBSI --- p.30Chapter 2.5 --- Results and Discussions --- p.31Chapter 2.6 --- Summary --- p.37Chapter 3 --- Multichannel Switching and Resequencing --- p.40Chapter 3.1 --- Introduction --- p.40Chapter 3.2 --- Channel Assignment --- p.41Chapter 3.2.1 --- VC-Based Channel Allocation Mechanism --- p.41Chapter 3.2.2 --- Port-Based Channel Allocation Mechanism --- p.45Chapter 3.2.3 --- Trunk-Based Channel Allocation Mechanism --- p.46Chapter 3.3 --- Resequencer --- p.50Chapter 3.3.1 --- Resequencing Algorithm --- p.50Chapter 3.4 --- Results and Discussion --- p.55Chapter 3.5 --- Summary --- p.60Chapter 4 --- Scheduling --- p.62Chapter 4.1 --- Introduction --- p.62Chapter 4.2 --- Virtual Clock Scheduling (VCS) --- p.62Chapter 4.3 --- Gated Virtual Clock Scheduling (GVCS) --- p.70Chapter 4.4 --- Time-Priority Model --- p.75Chapter 4.5 --- Programmable Rate-based Scheduler (PRS) --- p.80Chapter 4.6 --- Integration with Resequencer --- p.83Chapter 4.7 --- Results and Discussions --- p.86Chapter 4.8 --- Summary --- p.96Chapter 5 --- Conclusion --- p.99Bibliography --- p.10

Numerical aerodynamic simulation facility feasibility study

There were three major issues examined in the feasibility study. First, the ability of the proposed system architecture to support the anticipated workload was evaluated. Second, the throughput of the computational engine (the flow model processor) was studied using real application programs. Third, the availability reliability, and maintainability of the system were modeled. The evaluations were based on the baseline systems. The results show that the implementation of the Numerical Aerodynamic Simulation Facility, in the form considered, would indeed be a feasible project with an acceptable level of risk. The technology required (both hardware and software) either already exists or, in the case of a few parts, is expected to be announced this year. Facets of the work described include the hardware configuration, software, user language, and fault tolerance

Devices and networks for optical switching

This thesis is concerned with some aspects of the application of optics to switching and computing. Two areas are dealt with: the design of switching networks which use optical interconnects, and the development and application of the t-SEED optical logic device. The work on optical interconnects looks at the multistage interconnection network which has been proposed as a hybrid switch using both electronics and optics. It is shown that the architecture can be mapped from one dimensional to two dimensional format, so that the machine makes full use of the space available to the optics. Other mapping rules are described which allow the network to make optimum use of the optical interconnects, and the endpoint is a hybrid optical-electronic machine which should be able to outperform an all-electronic equivalent. The development of the t-SEED optical logic device is described, which is the integration of a phototransistor with a multiple quantum well optical modulator. It is found to be important to have the modulator underneath rather than on top of the transistor to avoid unwanted thyristor action. In order for the transistor to have a high gain the collector must have a low doping level, the exit window in the substrate must be etched all the way to the emitter layer, and the etch must not damage the emitter-base junction. A real optical gain of 1.6 has been obtained, which is higher than has ever been reached before but is not as high as should be possible. Improvements to the device are suggested. A new model of the Fabry-Perot cavity is introduced which helps considerably in the interpretation of experimental measurements made on the quantum well modulators. Also a method of improving the contrast of the multiple quantum well modulator by grading the well widths is proposed which may find application in long wavelength transmission modulators. Some systems which make use of the t-SEED are considered. It is shown that the t-SEED device has the right characteristics for use as a neuron element in the optical implementation of a neural network. A new image processing network for clutter removal in binary images is introduced which uses the t-SEED, and a brief performance analysis suggests that the network may be superior to an all-electronic machine

Smart Sensor Technologies for IoT

The recent development in wireless networks and devices has led to novel services that will utilize wireless communication on a new level. Much effort and resources have been dedicated to establishing new communication networks that will support machine-to-machine communication and the Internet of Things (IoT). In these systems, various smart and sensory devices are deployed and connected, enabling large amounts of data to be streamed. Smart services represent new trends in mobile services, i.e., a completely new spectrum of context-aware, personalized, and intelligent services and applications. A variety of existing services utilize information about the position of the user or mobile device. The position of mobile devices is often achieved using the Global Navigation Satellite System (GNSS) chips that are integrated into all modern mobile devices (smartphones). However, GNSS is not always a reliable source of position estimates due to multipath propagation and signal blockage. Moreover, integrating GNSS chips into all devices might have a negative impact on the battery life of future IoT applications. Therefore, alternative solutions to position estimation should be investigated and implemented in IoT applications. This Special Issue, “Smart Sensor Technologies for IoT” aims to report on some of the recent research efforts on this increasingly important topic. The twelve accepted papers in this issue cover various aspects of Smart Sensor Technologies for IoT

Future benefits and applications of intelligent on-board processing to VSAT services

The trends and roles of VSAT services in the year 2010 time frame are examined based on an overall network and service model for that period. An estimate of the VSAT traffic is then made and the service and general network requirements are identified. In order to accommodate these traffic needs, four satellite VSAT architectures based on the use of fixed or scanning multibeam antennas in conjunction with IF switching or onboard regeneration and baseband processing are suggested. The performance of each of these architectures is assessed and the key enabling technologies are identified

Adaptive control of communication networks using learning automata.

This research investigates communications network routing procedures, based on distributed learning automata concepts for circuit and packet switched networks. For this application, the learning automaton is shown to be an ideal adaptive control mechanism, with simple feedback and updating strategies which allow extremely practical implementations and perform very close to the desired optimum. In this thesis, the nature of learning automata routing schemes are explored by analytical and computer simulation techniques, primarily developing an elementary understanding of the automata routing and adaption process. Using simple circuit and message switched networks the conditions for minimum blocking probability and average delay are established and compared with the equilibrium behaviour of learning automata operating under alternative reinforcement algorithms. Later, large scale simulations of real networks are used to demonstrate and relate the learning automata scheme to existing routing techniques. These experiments, which are performed on sophisticated simulation packages produced for this study, take as examples hierarchical and general structured telephone networks and packet switched communications networks configured with both virtual call and datagram protocols. In addition, studies under failure mode conditions, including link, node and focussed overloads, conclusively demonstrate the superior performance afforded by the learning automata routing approach

Design study of Software-Implemented Fault-Tolerance (SIFT) computer

Software-implemented fault tolerant (SIFT) computer design for commercial aviation is reported. A SIFT design concept is addressed. Alternate strategies for physical implementation are considered. Hardware and software design correctness is addressed. System modeling and effectiveness evaluation are considered from a fault-tolerant point of view

On-board B-ISDN fast packet switching architectures. Phase 1: Study

The broadband integrate services digital network (B-ISDN) is an emerging telecommunications technology that will meet most of the telecommunications networking needs in the mid-1990's to early next century. The satellite-based system is well positioned for providing B-ISDN service with its inherent capabilities of point-to-multipoint and broadcast transmission, virtually unlimited connectivity between any two points within a beam coverage, short deployment time of communications facility, flexible and dynamic reallocation of space segment capacity, and distance insensitive cost. On-board processing satellites, particularly in a multiple spot beam environment, will provide enhanced connectivity, better performance, optimized access and transmission link design, and lower user service cost. The following are described: the user and network aspects of broadband services; the current development status in broadband services; various satellite network architectures including system design issues; and various fast packet switch architectures and their detail designs