MILO : a microarchitecture and logic optimizer

In this report we discuss strengths and weaknesses of logic synthesis systems and describe a system for microarchitectural and logic optimization. Our system uses a set of algorithms for synthesizing SSI/MSI macros from parameterized microarchitecture components. In addition, it uses rules for optimizing both at the microarchitecture and logic level. The system increases designer productivity and requires less design knowledge and experience from circuit engineers

Silicon compilation

Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory

LOT: Logic Optimization with Testability - new transformations for logic synthesis

A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools

Design of personalized location areas for future Pcs networks

In Global Systems for Mobile Communications (GSM), always-update location strategy is used to keep track of mobile terminals within the network. However future Personal Communication Networks (PCS) will require to serve a wide range of services (digital voice, video, data, and email) and also will have to support a large population of users. Under such demands, determining the exact location of a user by traditional strategies would be difficult and would result in increasing the signaling load imposed by location-update and paging procedures. The problem is not only in increasing cost, but also in non-efficient utilization of a precious resource, i.e., radio bandwidth; In this thesis, personalized Location Areas (PLAs) are formed considering the mobility patterns of individual users in the system such that the signaling due to location update and paging is minimized. We prove that the problem in this formulation is of NP complexity. Therefore we study efficient optimization techniques able to avoid combinatorial search. Three known classes of optimization techniques are studied. They are Simulated Annealing, Tabu Search and Genetic Search. Three algorithms are designed for solving the problem. Modeling does not assume any specific cell structure or network topology that makes the proposal widely applicable. The behavior of mobile terminals in the network is modeled as Random Walk with an absorbing state and the Markov chain is used for cost analysis; Numeric simulation carried out for 25 and 100 hexagonal cell networks have shown that Simulated Annealing based algorithm outperforms other two by indicators of the runtime complexity and signaling cost of location management. The ID\u27s of cells populating the calculated area are provided to the mobile terminal and saved in its local memory every time the mobile subscriber moves out its current location area. Otherwise, no location update is performed, but only paging. Thus, at the expense of small local memory, the location management is carried more efficiently

Sensor failure detection system

Advanced concepts for detecting, isolating, and accommodating sensor failures were studied to determine their applicability to the gas turbine control problem. Five concepts were formulated based upon such techniques as Kalman filters and a screening process led to the selection of one advanced concept for further evaluation. The selected advanced concept uses a Kalman filter to generate residuals, a weighted sum square residuals technique to detect soft failures, likelihood ratio testing of a bank of Kalman filters for isolation, and reconfiguring of the normal mode Kalman filter by eliminating the failed input to accommodate the failure. The advanced concept was compared to a baseline parameter synthesis technique. The advanced concept was shown to be a viable concept for detecting, isolating, and accommodating sensor failures for the gas turbine applications

Design of a fault tolerant airborne digital computer. Volume 2: Computational requirements and technology

This final report summarizes the work on the design of a fault tolerant digital computer for aircraft. Volume 2 is composed of two parts. Part 1 is concerned with the computational requirements associated with an advanced commercial aircraft. Part 2 reviews the technology that will be available for the implementation of the computer in the 1975-1985 period. With regard to the computation task 26 computations have been categorized according to computational load, memory requirements, criticality, permitted down-time, and the need to save data in order to effect a roll-back. The technology part stresses the impact of large scale integration (LSI) on the realization of logic and memory. Also considered was module interconnection possibilities so as to minimize fault propagation

Human-centered Electric Prosthetic (HELP) Hand

Through a partnership with Indian non-profit Bhagwan Mahaveer Viklang Sahayata Samiti, we designed a functional, robust, and and low cost electrically powered prosthetic hand that communicates with unilateral, transradial, urban Indian amputees through a biointerface. The device uses compliant tendon actuation, a small linear servo, and a wearable garment outfitted with flex sensors to produce a device that, once placed inside a prosthetic glove, is anthropomorphic in both look and feel. The prosthesis was developed such that future groups can design for manufacturing and distribution in India

Active FPGA Security through Decoy Circuits

Field Programmable Gate Arrays (FPGAs) based on Static Random Access Memory (SRAM) are vulnerable to tampering attacks such as readback and cloning attacks. Such attacks enable the reverse engineering of the design programmed into an FPGA. To counter such attacks, measures that protect the design with low performance penalties should be employed. This research proposes a method which employs the addition of active decoy circuits to protect SRAM FPGAs from reverse engineering. The effects of the protection method on security, execution time, power consumption, and FPGA resource usage are quantified. The method significantly increases the security of the design with only minor increases in execution time, power consumption, and resource usage. For the circuits used to characterize the method, security increased to more than one million times the original values, while execution time increased to at most 1.2 times, dynamic power consumption increased to at most two times, and look-up table usage increased to at most seven times the original values. These are reasonable penalties given the size and security of the modified circuits. The proposed design protection method also extends to FPGAs based on other technologies and to Application-Specific Integrated Circuits (ASICs). In addition to the design methodology proposed, a new classification of tampering attacks and countermeasures is presented

The implication of the hyperbolic discount model for annuitisation decisions

The low demand for immediate annuities at retirement has been a long-standing puzzle. We show that a hyperbolic discount model can explain this behaviour and results in the attractiveness of long-term deferred annuities. With a set of benchmark assumptions, we find that retirees would be willing to pay a much higher price than the actuarial fair price for annuities with longer deferred periods. Moreover, if governments were to introduce a pre-commitment device which requires pensioners to make annuitisation decisions around ten years before retirement, the take up rate of annuities could become higher

Fault-tolerant computer study

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed