718 research outputs found
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Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications
High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of todayโs petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.052 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator
An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems
The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works
Millimeter-wave Communication and Radar Sensing โ Opportunities, Challenges, and Solutions
With the development of communication and radar sensing technology, people are able to seek for a more convenient life and better experiences. The fifth generation (5G) mobile network provides high speed communication and internet services with a data rate up to several gigabit per second (Gbps). In addition, 5G offers great opportunities of emerging applications, for example, manufacture automation with the help of precise wireless sensing. For future communication and sensing systems, increasing capacity and accuracy is desired, which can be realized at millimeter-wave spectrum from 30 GHz to 300 GHz with several tens of GHz available bandwidth. Wavelength reduces at higher frequency, this implies more compact transceivers and antennas, and high sensing accuracy and imaging resolution. Challenges arise with these application opportunities when it comes to realizing prototype or demonstrators in practice. This thesis proposes some of the solutions addressing such challenges in a laboratory environment.High data rate millimeter-wave transmission experiments have been demonstrated with the help of advanced instrumentations. These demonstrations show the potential of transceiver chipsets. On the other hand, the real-time communication demonstrations are limited to either low modulation order signals or low symbol rate transmissions. The reason for that is the lack of commercially available high-speed analog-to-digital converters (ADCs); therefore, conventional digital synchronization methods are difficult to implement in real-time systems at very high data rates. In this thesis, two synchronous baseband receivers are proposed with carrier recovery subsystems which only require low-speed ADCs [A][B].Besides synchronization, high-frequency signal generation is also a challenge in millimeter-wave communications. The frequency divider is a critical component of a millimeter-wave frequency synthesizer. Having both wide locking range and high working frequencies is a challenge. In this thesis, a tunable delay gated ring oscillator topology is proposed for dual-mode operation and bandwidth extension [C]. Millimeter-wave radar offers advantages for high accuracy sensing. Traditional millimeter-wave radar with frequency-modulated continuous-wave (FMCW), or continuous-wave (CW), all have their disadvantages. Typically, the FMCW radar cannot share the spectrum with other FMCW radars.\ua0 With limited bandwidth, the number of FMCW radars that could coexist in the same area is limited. CW radars have a limited ambiguous distance of a wavelength. In this thesis, a phase-modulated radar with micrometer accuracy is presented [D]. It is applicable in a multi-radar scenario without occupying more bandwidth, and its ambiguous distance is also much larger than the CW radar. Orthogonal frequency-division multiplexing (OFDM) radar has similar properties. However, its traditional fast calculation method, fast Fourier transform (FFT), limits its measurement accuracy. In this thesis, an accuracy enhancement technique is introduced to increase the measurement accuracy up to the micrometer level [E]
A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects
Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2
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High Performance Local Oscillator Design for Next Generation Wireless Communication
Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances.
The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication.
The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges.
To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen-
eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation.
To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept.
In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes.
Finally, Chapter 6 presents the conclusion of this thesis
Design Techniques for Energy Efficient Multi-GB/S Serial I/O Transceivers
Total I/O bandwidth demand is growing in high-performance systems due to the emergence of many-core microprocessors and in mobile devices to support the next generation of multi-media features. High-speed serial I/O energy efficiency must improve in order to enable continued scaling of these parallel computing platforms in applications ranging from data centers to smart mobile devices.
The first work, a low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase filter. The output driver voltage swing is accurately controlled from 100-200 mV_(ppd) using a low-voltage pseudo-differential regulator that employs a partial negative-resistance load for improved low frequency gain. 1:8 input de-multiplexing is performed at the receiver equalizer output with 8 parallel input samplers clocked from an 8-phase injection-locked oscillator that provides more than 1UI de-skew range.
Low-power high-speed serial I/O transmitters which include equalization to compensate for channel frequency dependent loss are required to meet the aggressive link energy efficiency targets of future systems. The second work presents a low power serial link transmitter design that utilizes an output stage which combines a voltage-mode driver, which offers low static-power dissipation, and current-mode equalization, which offers low complexity and dynamic-power dissipation. The utilization of current-mode equalization decouples the equalization settings and termination impedance, allowing for a significant reduction in pre-driver complexity relative to segmented voltage-mode drivers. Proper transmitter series termination is set with an impedance control loop which adjusts the on-resistance of the output transistors in the driver voltage-mode portion. Further reductions in dynamic power dissipation are achieved through scaling the serializer and local clock distribution supply with data rate.
Finally, it presents that a scalable quarter-rate transmitter employs an analog-controlled impedance-modulated 2-tap voltage-mode equalizer and achieves fast power-state transitioning with a replica-biased regulator and ILO clock generation. Capacitively-driven 2 mm global clock distribution and automatic phase calibration allows for aggressive supply scaling
Source-synchronous I/O Links using Adaptive Interface Training for High Bandwidth Applications
Mobility is the key to the global business which requires people to be always connected to a central server. With the exponential increase in smart phones, tablets, laptops, mobile traffic will soon reach in the range of Exabytes per month by 2018. Applications like
video streaming, on-demand-video, online gaming, social media applications will further increase the traffic load. Future application scenarios, such as Smart Cities, Industry 4.0, Machine-to-Machine (M2M) communications bring the concepts of Internet of Things (IoT) which requires high-speed low power communication infrastructures. Scientific applications, such as space exploration, oil exploration also require computing speed in the range of Exaflops/s by 2018 which means TB/s bandwidth at each memory node. To
achieve such bandwidth, Input/Output (I/O) link speed between two devices needs to be increased to GB/s.
The data at high speed between devices can be transferred serially using complex Clock-Data-Recovery (CDR) I/O links or parallely using simple source-synchronous I/O links. Even though CDR is more efficient than the source-synchronous method for single I/O link, but to achieve TB/s bandwidth from a single device, additional I/O links will be required and the source-synchronous method will be more advantageous in terms of area and power requirements as additional I/O links do not require extra hardware resources. At high speed, there are several non-idealities (Supply noise, crosstalk, Inter-
Symbol-Interference (ISI), etc.) which create unwanted skew problem among parallel source-synchronous I/O links. To solve these problems, adaptive trainings are used in time domain to synchronize parallel source-synchronous I/O links irrespective of these non-idealities.
In this thesis, two novel adaptive training architectures for source-synchronous I/O links are discussed which require significantly less silicon area and power in comparison to state-of-the-art architectures. First novel adaptive architecture is based on the unit delay concept to synchronize two parallel clocks by adjusting the phase of one clock in only one direction. Second novel adaptive architecture concept consists of Phase Interpolator (PI)-based Phase Locked Loop (PLL) which can adjust the phase in both direction and
achieve faster synchronization at the expense of added complexity. With an increase in parallel I/O links, clock skew which is generated by the improper clock tree, also affects the timing margin. Incorrect duty cycle further reduces the timing margin mainly in Double Data Rate (DDR) systems which are generally used to increase the bandwidth of a high-speed communication system. To solve clock skew and duty cycle problems, a novel clock tree buffering algorithm and a novel duty cycle corrector are described which further reduce the power consumption of a source-synchronous system
Clocking and Skew-Optimization For Source-Synchronous Simultaneous Bidirectional Links
There is continuous expansion of computing capabilities in mobile devices which
demands higher I/O bandwidth and dense parallel links supporting higher data rates. Highspeed
signaling leverages technology advancements to achieve higher data rates but is limited
by the bandwidth of the electrical copper channel which have not scaled accordingly.
To meet the continuous data-rate demand, Simultaneous Bi-directional (SBD) signaling
technique is an attractive alternative relative to uni-directional signaling as it can work at
lower clock speeds, exhibits better spectral efficiency and provides higher throughput in
pad limited PCBs.
For low-power and more robust system, the SBD transceiver should utilize forwarded
clock system and per-pin de-skew circuits to correct the phase difference developed
between the data and clock. The system can be configured in two roles, master and
slave. To save more power, the system should have only one clock generator. The master
has its own clock source and shares its clock to the slave through the clock channel, and the
slave uses this forwarded clock to deserialize the inbound data and serialize the outbound
data. A clock-to-data skew exists which can be corrected with a phase tracking CDR. This
thesis presents a low-power implementation of forwarded clocking and clock-to-data skew
optimization for a 40 Gbps SBD transceiver. The design is implemented in 28nm CMOS
technology and consumes 8.8mW of power for 20 Gbps NRZ data at 0.9 V supply. The
area occupied by the clocking 0.018 mm^2 area
ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ ๊ธฐ๋ฐ ๊ธฐ์ค ์ฃผํ์๋ฅผ ์ฌ์ฉํ์ง ์๋ ํด๋ก ๋ฐ ๋ฐ์ดํฐ ๋ณต์ ํ๋ก์ ์ค๊ณ ๋ฐฉ๋ฒ๋ก
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022. 8. ์ ๋๊ท .In this thesis, a design of a high-speed, power-efficient, wide-range clock and data recovery (CDR) without a reference clock is proposed. A frequency acquisition scheme using a stochastic frequency detector (SFD) based on the Alexander phase detector (PD) is utilized for the referenceless operation. Pat-tern histogram analysis is presented to analyze the frequency acquisition behavior of the SFD and verified by simulation. Based on the information obtained by pattern histogram analysis, SFD using autocovariance is proposed. With a direct-proportional path and a digital integral path, the proposed referenceless CDR achieves frequency lock at all measurable conditions, and the measured frequency acquisition time is within 7ฮผs. The prototype chip has been fabricated in a 40-nm CMOS process and occupies an active area of 0.032 mm2. The proposed referenceless CDR achieves the BER of less than 10-12 at 32 Gb/s and exhibits an energy efficiency of 1.15 pJ/b at 32 Gb/s with a 1.0 V supply.๋ณธ ๋
ผ๋ฌธ์ ๊ธฐ์ค ํด๋ญ์ด ์๋ ๊ณ ์, ์ ์ ๋ ฅ, ๊ด๋์ญ์ผ๋ก ๋์ํ๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก์ ์ค๊ณ๋ฅผ ์ ์ํ๋ค. ๊ธฐ์ค ํด๋ญ์ด ์๋ ๋์์ ์ํด์ ์๋ ์ฐ๋ ์์ ๊ฒ์ถ๊ธฐ์ ๊ธฐ๋ฐํ ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ๋ฅผ ์ฌ์ฉํ๋ ์ฃผํ์ ํ๋ ๋ฐฉ์์ด ์ฌ์ฉ๋๋ค. ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ์ ์ฃผํ์ ์ถ์ ์์์ ๋ถ์ํ๊ธฐ ์ํด ํจํด ํ์คํ ๊ทธ๋จ ๋ถ์ ๋ฐฉ๋ฒ๋ก ์ ์ ์ํ์๊ณ ์๋ฎฌ๋ ์ด์
์ ํตํด ๊ฒ์ฆํ์๋ค. ํจํด ํ์คํ ๊ทธ๋จ ๋ถ์์ ํตํด ์ป์ ์ ๋ณด๋ฅผ ๋ฐํ์ผ๋ก ์๊ธฐ๊ณต๋ถ์ฐ์ ์ด์ฉํ ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ๋ฅผ ์ ์ํ๋ค. ์ง์ ๋น๋ก ๊ฒฝ๋ก์ ๋์งํธ ์ ๋ถ ๊ฒฝ๋ก๋ฅผ ํตํด ์ ์๋ ๊ธฐ์ค ํด๋ญ์ด ์๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก๋ ๋ชจ๋ ์ธก์ ๊ฐ๋ฅํ ์กฐ๊ฑด์์ ์ฃผํ์ ์ ๊ธ์ ๋ฌ์ฑํ๋ ๋ฐ ์ฑ๊ณตํ์๊ณ , ๋ชจ๋ ๊ฒฝ์ฐ์์ ์ธก์ ๋ ์ฃผํ์ ์ถ์ ์๊ฐ์ 7ฮผs ์ด๋ด์ด๋ค. 40-nm CMOS ๊ณต์ ์ ์ด์ฉํ์ฌ ๋ง๋ค์ด์ง ์นฉ์ 0.032 mm2์ ๋ฉด์ ์ ์ฐจ์งํ๋ค. ์ ์ํ๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก๋ 32 Gb/s์ ์๋์์ ๋นํธ์๋ฌ์จ 10-12 ์ดํ๋ก ๋์ํ์๊ณ , ์๋์ง ํจ์จ์ 32Gb/s์ ์๋์์ 1.0V ๊ณต๊ธ์ ์์ ์ฌ์ฉํ์ฌ 1.15 pJ/b์ ๋ฌ์ฑํ์๋ค.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 13
CHAPTER 2 BACKGROUNDS 14
2.1 CLOCKING ARCHITECTURES IN SERIAL LINK INTERFACE 14
2.2 GENERAL CONSIDERATIONS FOR CLOCK AND DATA RECOVERY 24
2.2.1 OVERVIEW 24
2.2.2 JITTER 26
2.2.3 CDR JITTER CHARACTERISTICS 33
2.3 CDR ARCHITECTURES 39
2.3.1 PLL-BASED CDR โ WITH EXTERNAL REFERENCE CLOCK 39
2.3.2 DLL/PI-BASED CDR 44
2.3.3 PLL-BASED CDR โ WITHOUT EXTERNAL REFERENCE CLOCK 47
2.4 FREQUENCY ACQUISITION SCHEME 50
2.4.1 TYPICAL FREQUENCY DETECTORS 50
2.4.1.1 DIGITAL QUADRICORRELATOR FREQUENCY DETECTOR 50
2.4.1.2 ROTATIONAL FREQUENCY DETECTOR 54
2.4.2 PRIOR WORKS 56
CHAPTER 3 DESIGN OF THE REFERENCELESS CDR USING SFD 58
3.1 OVERVIEW 58
3.2 PROPOSED FREQUENCY DETECTOR 62
3.2.1 MOTIVATION 62
3.2.2 PATTERN HISTOGRAM ANALYSIS 68
3.2.3 INTRODUCTION OF AUTOCOVARIANCE TO STOCHASTIC FREQUENCY DETECTOR 75
3.3 CIRCUIT IMPLEMENTATION 83
3.3.1 IMPLEMENTATION OF THE PROPOSED REFERENCELESS CDR 83
3.3.2 CONTINUOUS-TIME LINEAR EQUALIZER (CTLE) 85
3.3.3 DIGITALLY-CONTROLLED OSCILLATOR (DCO) 87
3.4 MEASUREMENT RESULTS 89
CHAPTER 4 CONCLUSION 99
APPENDIX A DETAILED FREQUENCY ACQUISITION WAVEFORMS OF THE PROPOSED SFD 100
BIBLIOGRAPHY 108
์ด ๋ก 122๋ฐ
Design and modelling of clock and data recovery integrated circuit in 130 nm CMOS technology for 10 Gb/s serial data communications
This thesis describes the design and implementation of a fully monolithic 10 Gb/s phase and frequency-locked loop based clock and data recovery (PFLL-CDR) integrated circuit, as well as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The proposed design was implemented and fabricated using the 130 nm CMOS technology offered by UMC (United Microelectronics Corporation). Different PLL-based CDR circuits topologies were investigated in terms of architecture and speed. Based on the investigation, we proposed a new concept of quarter-rate (i.e. the clocking speed in the circuit is 2.5 GHz for 10 Gb/s data rate) and dual-loop topology which consists of phase-locked and frequency-locked loop. The frequency-locked loop (FLL) operates independently from the phase-locked loop (PLL), and has a highly-desired feature that once the proper frequency has been acquired, the FLL is automatically disabled and the PLL will take over to adjust the clock edges approximately in the middle of the incoming data bits for proper sampling. Another important feature of the proposed quarter-rate concept is the inherent 1-to-4 demultiplexing of the input serial data stream. A new quarter-rate phase detector based on the non-linear early-late phase detector concept has been used to achieve the multi-Giga bit/s speed and to eliminate the need of the front-end data pre-processing (edge detecting) units usually associated with the conventional CDR circuits. An eight-stage differential ring oscillator running at 2.5 GHz frequency center was used for the voltage-controlled oscillator (VCO) to generate low-jitter multi-phase clock signals. The transistor level simulation results demonstrated excellent performances in term of locking speed and power consumption. In order to verify the accuracy of the proposed quarter-rate concept, a clockless asynchronous serial link incorporating the proposed concept and communicating two chips at 10 Gb/s has been modelled at gate level using the Verilog-A language and time-domain simulated
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