A Design Approach for Networks of Self-Sampled All-Digital Phase-Locked Loops

International audienceThis paper addresses the problem of the stability and the performance analysis of N-nodes Cartesian networks of self-sampled all digital phase-locked loops. It can be demonstrated that under certain conditions (such as filter coefficients value) a global and a local synchronization can be obtained. Our approach to find the optimal conditions consists in analyzing an corresponding linear average system of the Cartesian network rather than constructing a piecewise-linear system which is extremely difficult to analysis. The constructed corresponding system takes into account the non-linearity of the network and especially the self-sampling property. It is then analyzed by linear performance criteria such as modulus margin to guarantee a robust stability of the Cartesian network. The reliability of our approach is proved by transient simulations in networks of different sizes

Synchronized State in Networks of Digital Phase-Locked Loops

International audienceClock distribution networks of synchronized oscillators are an alternative approach to classical tree-like clock distribution methods. Each node of the network may consist of a phase-locked loop (PLL) trying to match the phase of its neighbors. Then a network of independent oscillators takes the place of the centralized clock source, providing separate clock signals to the physically distant parts of the system. In the discrete case, the digital filter is necessarily operated asynchronously: each operation is triggered by a rising edge of the locally-generated clock, the frequency and phase of which vary as the whole system tries to synchronize. The locking behavior, the synchronous state and the stability conditions of such a system are analyzed. Similarly, the synchronization of an autonomous network of two self-sampled PLLs is studied. Surprisingly, its analysis is much simpler than that of the single PLL

Programmable rate modem utilizing digital signal processing techniques

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam

A novel maximal-length sequence synchronisation network

Spread Spectrum has become a popular digital modulation scheme in recent years. The advantages the scheme offers, at the expense of bandwidth, make it attractive in a multitude of commercial applications. The most common method, and the one of interest in this thesis, of generating Spread Spectrum is multiplying the data waveform by a wideband, digitally generated waveform. This is referred to as Direct Sequence Spread Spectrum. The characteristics of Spread Spectrum systems are determined by the spreading waveform. A common group of spreading waveforms, and the ones dealt with in this text, are the maximal-length sequences. These are a class of pseudorandom waveforms. Their properties include a two valued autocorrelation function with its maximum value at no code-phase offset. This allows for multiple access to a single resource and the suppression of multi-path interference as adjacent codes have little effect on each other. This same property requires that the receiver must accurately align its replica of the spreading waveform to the transmitted waveform in order to despread the received waveform and demodulate the data. Common methods of synchronisation use a two pronged solution. Firstly the correct code phase is determined. This is referred to as code acquisition. Secondly the clocking frequency of the received waveform must be resolved in order to precisely align the two sequences. This is referred to as code tracking. Receivers therefore tend to be complex and expensive. This thesis involved the investigation of two pseudo-noise synchronisation networks proposed by J .G. van de Groenendaal. These networks offered both code acquisition and tracking in a single robust loop. The investigation, done in co-operation with J..G. van de Groenendaal, persued two avenues. Firstly the loops were simulated. This method allows for the easy alteration of system parameters. Valuable insight into the loop dynamics can thus be gained. Secondly the loops were built on the bench. This allows for the practical confirmation of the results of the simulation. Both synchronisation loops were based on variations of the maximal likelihood phase detector. This phase detector is formed by taking the product of the first derivative with respect to time of the receiver's replica of the transmitted waveform and the received waveform. The initial investigation involved calculating the phase information generated by this phase discriminator for a variety of code-phase and frequency offsets. It was found that there were two stable points in the baseband Spread Spectrum search grid, a grid where a cell consists of a certain code-phase and frequency offset. These stable points existed at no frequency offset, which means that the loops should track the input frequency, and a one or no code-phase offset, which means that the loops should acquire either code-phase. A simple model where the novel synchronisation loop's conditions are represented by a 'ball' resting on the baseband Spread Spectrum search grid as expressed in terms of the integrated phase output of the maximal likelihood phase discriminator was developed. In this model the 'ball' will roll around the surface until one of the two stable points is entered. This describes quite accurately the paths the novel synchronisation loop does in fact take through the baseband Spread Spectrum search grid. The first loop is based directly on the maximal likelihood phase detector. The differentiator is thus in the feedback path of the loop. This results in the loop being unstable and parameter sensitive. Moving the differentiator into the input path, as in the second loop, resulted in a more stable loop. This loop therefore offered a complete, simple synchronisation solution. The novel synchronisation loop with the differentiator in the input path was found to operate at signal-to- noise ratios of -2 dB. Improvement of this signal-to-noise ratio does not offer any advantages in a Spread Spectrum environment as the loop needs to work in a coherent system where the radio frequency carrier must be resolved before the receiver's pseudo-noise sequence can be synchronised. A radio frequency carrier cannot be easily resolved at signal-to-noise ratios lower than O dB. The loop was further adapted to operate in the data environment. Under conditions of data modulation the received waveform is randomly inverted by the data. This results in the loop being driven out of lock. The phase discriminator's slope, having locked on a certain polarity, cannot track an input of the opposite polarity. The loop was adapted by including detection circuitry that would monitor the state of the receiver with respect to the incoming data waveform and alter the polarity of the of the discriminator's slope where necessary. During the prototyping of the loop on the bench certain implementations were investigated. These included the signed edge detector, a wideband low noise implementation of a square wave differentiator, and the synchronous oscillator, a form of injection locked oscillator. The loop was shown to achieve synchronisation. The novel synchronisation loop with the differentiator in the input path is thus capable of synchronising two maximal-length sequences in both code-phase and frequency

Application of Random Walk Model for Timing Recovery in Modern Mobile SATCOM Systems

In a modern mobile satellite communication (SATCOM) system, a ground terminal receiver receives a radio frequency signal that is demodulated to generate a baseband digital signal waveform containing a self-clocking bit stream of digital data. The received baseband digital signal waveform is recovered and tracked using a timing recovery loop (TRL). The traditional TRLs use early-and-late gates, digital transition tracking, filter-and-square, and delay-and-multiply functions. In bit timing detection, the bit stream is self-clocking and the timing differential dithers about correct bit timing in the TRLs. For mobile satellite communication environments, the traditional TRLs drop lock when the loop signal-to-noise ratio (SNR) is smaller than a threshold value or the residual Doppler frequency is larger than the operating loop bandwidth. After dropping lock, the traditional TRLs experience long hang up time due to the need to reacquire the timing pulses. Recently, random walk filters (RWF) have been adapted to improve the bit clock locking stability and are applied to recover bit timing information of a digital data stream. This chapter describes random walk model for timing jitter and discusses how RWF solution can address the timing recovery challenges in mobile satellite communication environments

Techniques for Efficient Spectrum Sensing in Heterogeneous Wireless Networks

Spectrum sensing is one of the most challenging and complex task in cognitive radio and it should be often performed by mobile devices with a limited battery life. So the development of efficient techniques for advanced spectrum sensing in heterogeneous, ad hoc environments, such as those in emergency situations, is of crucial importance. In this context spectrum sensing can be completed by the determination of the spatial coordinates of the devices in order to achieve the full potential of ad hoc networks management. In this work we present two techniques for improving the efficiency of mobile devices involved in spatial spectrum sensing: design of efficacious frequency synthesizers and hybrid localization for saving energy in the tracking process. Among the different frequency synthesis techniques, we focus on the phase-locked loop (PLL) approach and we consider the optimization of the loop filter for the PLL in the light of Wiener theory by taking into account the phase noise affecting the incoming carrier, the additive white Gaussian noise and the self-noise produced by the phase detector. Then we show an approach for improving the trade-off between energy consumption and performance in a localization tracking process, realized mixing active signal transmissions as well as passive signal reflections

Implementation of a Software Defined Spread Spectrum Communication System

The goal of this thesis is to develop a framework to prototype a software defined direct sequence spread spectrum transceiver that can be used as a node in an ad hoc network. We introduce the concept of a software radio, the current state of art, and GNU Radio and its concepts. We discuss in detail the design and development methods of GNU Radio and develop a flowgraph in Python to demonstrate the method of development. We present a mathematical analysis of (DSSS) modulation and demodulation schemes along with the transmitter and receiver design. We use this design to develop an analogous design in GNU Radio using the signal processing blocks that are present in GNU Radio and ones we develop. We perform simulations and tests to validate the algorithms, signal processing blocks and flowgraphs that we developed. We find that the signal acquistion algorithm is capable of determining the code and frequency offset in a received (DSSS) signal. We also find that the carrier tracking loop is capable of tracking the received carrier when the signal has a high (SNR). We conclude that GNU Radio as a technology can be used to prototype transceivers that are highly configurable and expandable. Finally, we identify and suggest some possible areas where this design can be developed and improved further

Distributed Beamforming of Two Autonomous Transmitters

The distributed beamformer is a scheme which provides spatial diversity to combat the undesired effects of the wireless channel. The distributed beamformer requires strict carrier frequency and phase synchronization in order to maximize SNR at a destination for fixed transmit powers. This project investigated the synchronization of two such transmitters in a wired single path channel with off-the-shelf integrated circuits. Additionally, a stable hardware platform for an acoustic (wireless) implementation of such a distributed beamformer was provided